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(R)
82C931 Plug and Play Integrated Audio Controller Data Book
912-3000-035 Revision: 2.1 August 1, 1997
Copyright
Copyright (c) 1996, OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of OPTi Incorporated, 888 Tasman Drive, Milpitas, CA 95035.
Disclaimer
OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and especially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, OPTi Inc. reserves the right to revise the design and associated documentation and to make changes from time to time in the content without obligation of OPTi Inc. to notify any person of such revisions or changes.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Incorporated. All other trademarks and copyrights are the property of their respective holders.
OPTi Inc.
888 Tasman Drive Milpitas, CA 95035 Tel: (408) 486-8000 Fax: (408) 486-8001 WWW: http://www.opti.com/
82C931 Table of Contents
1.0 2.0 3.0 Features ............................................................................................................................ 1 Overview ........................................................................................................................... 3 Signal Definitions ............................................................................................................. 5
3.1 3.2 Mode Selection ................................................................................................................................... 5 931-MB Mode....................................................................................................................................... 6 3.2.1 931-MB Mode Signal Descriptions ......................................................................................... 8 3.2.1.1 ISA Bus Interface Signals ....................................................................................... 8 3.2.1.2 MIDI Interface Signals............................................................................................. 8 3.2.1.3 Configuration and External PnP EEPROM Interface Signals ................................. 9 3.2.1.4 Game Port and Serial Audio Interface Signals ....................................................... 9 3.2.1.5 Codec/Mixer Interface Signals ..............................................................................10 3.2.1.6 Power and Ground Pins ........................................................................................11
3.3
931-AD Mode .....................................................................................................................................12 3.3.1 931-AD Mode Signal Descriptions........................................................................................14 3.3.1.1 ISA Bus Signals ....................................................................................................14 3.3.1.2 MIDI Interface Signals...........................................................................................14 3.3.1.3 Configuration, External PnP EEPROM, and IDE CD-ROM Interface Signals.......15 3.3.1.4 Game Port and Modem Interface Signals .............................................................16 3.3.1.5 Codec/Mixer Interface Signals ..............................................................................16 3.3.1.6 Serial Audio Interface Signals ...............................................................................17 3.3.1.7 Power and Ground Pins ........................................................................................17
4.0
Functional Description .................................................................................................. 19
4.1 4.2 Plug and Play ....................................................................................................................................19 16-Bit Codec/Mixer ...........................................................................................................................20 4.2.1 4.2.2 4.3 4.4 4.5 4.6 4.7 4.8 Codec ...................................................................................................................................20 Mixer.....................................................................................................................................21
Frequency Synthesizer ....................................................................................................................22 16-Bit Type F DMA Playback ...........................................................................................................23 Modem Interface ...............................................................................................................................23 Push Button Volume Control...........................................................................................................23 External Serial EEPROM ..................................................................................................................23 Serial Audio Interface .......................................................................................................................23 4.8.1 4.8.2 I2S-justified format and its variations....................................................................................23 Sony format ..........................................................................................................................24
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Table of Contents (cont.)
4.8.3 4.8.4 4.8.5 4.8.6 AT&T PCM codec T7525 compatible 16-bit mono format ....................................................24 Testing I2S format (ZV port) with Audio Precision machine .................................................24 Relevant MC register settings ..............................................................................................24 ZV-Port I2S...........................................................................................................................25 4.8.6.1 LRCLK ..................................................................................................................25 4.8.6.2 SDATA ..................................................................................................................25 4.8.6.3 SCLK.....................................................................................................................26 4.8.6.4 MCLK ....................................................................................................................26 Advanced Precision General Purpose Serial Port................................................................26 TDA1311 Stereo Continuous Calibration .............................................................................27
4.8.7 4.8.8
5.0
Register Descriptions .................................................................................................... 29
5.1 5.2 5.3 5.4 I/O Base Addresses ..........................................................................................................................29 MCBase Register .............................................................................................................................29 SBBase Register...............................................................................................................................36 WSBase Register ..............................................................................................................................37
6.0
Electrical Specifications................................................................................................ 45
6.1 6.2 6.3 6.4 6.5 6.6 Absolute Maximum Ratings.............................................................................................................45 DC Characteristics: 5.0 Volt (VCC = 5.0V 5%, TA = 0C to +70C)..............................................45 General Specifications: 5.0 Volt (VCC = 5.0V 5%, TA = 0C to +70C) .......................................46 Pin Specifications - Analog (VCC = 5.0V, 25xC) ............................................................................47 Volume Setting..................................................................................................................................47 Analog Characteristics.....................................................................................................................47 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.7 Analog Inputs........................................................................................................................48 Analog Outputs (10kW, 25pF) ..............................................................................................48 Volume Settings ...................................................................................................................48 Analog-to-Digital Converters ................................................................................................49 Digital-to-Analog Converters ................................................................................................49
AC Timings ........................................................................................................................................49
7.0
Mechanical Packages .................................................................................................... 53
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82C931 List of Figures
Figure 1-1 Figure 2-1 Figure 2-2 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 7-1 Figure 7-2 System Block Diagram .................................................................................................................... 1 Functional Block Diagram................................................................................................................ 3 Data Flow Block Diagram ................................................................................................................ 4 931-MB Mode PQFP Pin Diagram.................................................................................................. 6 931-AD Mode PQFP Pin Diagram .................................................................................................12 Functional Block Diagram..............................................................................................................20 Mixer Block Diagram .....................................................................................................................21 I2S Format .....................................................................................................................................25 General Purpose Serial Port, Timing Relationships ......................................................................26 Format of Input Signals .................................................................................................................27 RESET and CLK Timing Waveform...............................................................................................50 CD-ROM I/O Read Cycle...............................................................................................................51 CD-ROM I/O Write Cycle...............................................................................................................51 DMA Write/Playback Cycle............................................................................................................52 DMA Read/Capture Cycle .............................................................................................................52 100-pin PQFP, Plastic Quad Flat Pack .........................................................................................53 100-pin TQFP, Thin Quad Flat Package .......................................................................................54
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82C931 List of Tables
Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 4-1 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Mode Selection ................................................................................................................................ 5 Mode Features ................................................................................................................................ 5 Signal Definitions Legend ................................................................................................................ 5 931-MB Mode Numerical Pin Cross-Reference List ........................................................................ 7 931-MB Mode Alphabetical Pin Cross-Reference List..................................................................... 7 931-AD Mode Numerical Pin Cross-Reference List ......................................................................13 931-AD Mode Alphabetical Pin Cross-Reference List ...................................................................13 FS Output Frequencies .................................................................................................................22 82C931 I/O Base Addresses .........................................................................................................29 82C931 Register Map....................................................................................................................29 MCBase, Direct MC Register.........................................................................................................30 McBase, Index (MCIndx) and Data (MCData) Ports Address Range............................................30 MCIdx and MCData Registers .......................................................................................................30 MC Indirect Registers ....................................................................................................................31 SBBase Registers for FM and DAP Applications ..........................................................................36 WSBase Registers for Windows Sound System Applications .......................................................37 WSBase Register for Codec/Mixer Applications............................................................................38 Codec Indirect Registers ...............................................................................................................40 Expanded Mode CIR .....................................................................................................................43
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OPTi Confidential
82C931
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82C931 Plug and Play Integrated Audio Controller
Features
* Full duplex operation: record and playback simultaneously using two 8- or 16-bit DMA channels * Supports IMA ADPCM, -law, A-law decompression * 8- or 16-bit stereo sound data up to 48KHz stereo
* Integrated sound controller compatible with: - Sound Blaster ProTM - Ad LibTM - Microsoft(R) WindowsTM Sound SystemTM * Microsoft(R) PC-97 compliant * Built-in high-quality 22 voice, 52 operator, OPTiFMTM music synthesizer with enhanced bass * Built-in 7-channel mixer: five stereo, two mono * Built-in 16-bit sigma-delta stereo codec * ISA Plug and Play Specification 1.0a compatible, supports a maximum of six logical devices: - Sound Blaster Pro, Windows Sound System, FM synthesis - MPU-401 MIDI interface - CD-ROM interface - Joystick/game port - Modem interface - 82C931 control * Supports external serial EEPROM (optional) * External modem chipset interface
* Supports 16-bit Type F DMA playback, accelerates telephony-audio applications * Digital joystick interface support, improves responsiveness (Microsoft SideWinderTM) * I2S serial interface supports Zoom Video Port, wavetable controller and modem chipset * DirectSoundTM interface support * Power-down modes * Silence mode to turn-off all audio functions * Hardware and software volume control via push-button interface * 100-pin PQFP (Plastic Quad Flat Pack) * 100-pin TQFP (Thin Quad Flat Pack)
Figure 1-1
System Block Diagram
Speaker Analog Interface ISA Bus
OPTi 82C931
Line-Out Line-In CD Audio Microphone
IDE CD-ROM Interface Modem Interface Joystick Port, MIDI Port I2S Serial Audio Port
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82C931
2.0 Overview
MIDI interface, Windows Sound System interface, FM synthesizer interface, 16-bit codec/mixer, game port timer, and IDE CD-ROM interface. The device also includes dual DMA channels that support full duplex operation for simultaneous record and playback, a silence mode, power-down modes, and software programmable interrupts. (Figure 2-1 shows a functional block diagram of the 82C931. Figure 2-2 shows the 82C931 data flow block diagram.) The 82C931 Integrated Audio Controller provides all of the functions and interfaces for Sound Blaster Pro-compatible and Microsoft Windows Sound System-compatible cards. The 82C931 is intended to provide an integrated audio solution for business audio, educational/entertainment sound, and multimedia applications.
The OPTi 82C931 is a single-chip Plug-and-Play audio system controller and codec that provides compatibility with Sound Blaster ProTM, Microsoft Windows Sound SystemTM, OPL3, and MPU-401 interfaces. The 82C931 integrates a 16bit stereo sigma-delta codec and PC-97 compliant internal resource structure. This provides an effective audio solution for Windows 95 operating systems, DirectSoundTM, and advanced audio applications. The 82C931 provides front panel push-button volume control, external modem chip interface, serial EEPROM for further customizing, support for 16-bit Type F DMA playback and an I2S serial interface to a Zoom Video Port, wavetable controller, or modem chipset. The 82C931 includes the following functions: ISA bus interface, Sound Blaster Pro-compatible Digital Audio Processor,
Figure 2-1
Functional Block Diagram
IOW# IOR# AEN RESET OSCI SA[15:0] SD[15:0] or SD[7:0] SDHOE+GPIO0 DACK0#/1#/3# DACK5#/6# DRQ0/1/3 IRQ3/4/5/7/9/10/11/15 GD[7:0] OSCI OSCO MICL/R AUXL/R CDL/R LINEL/R OUTL/R MIXOUTL/R VOLUP VOLDWN SADI SADO SCLK FSYNC
ISA Control
WSS REGS
CLK GEN CONF REGS
Digital Audio Processor
8/16-bit Type DMA Logic
FIFO
RXD
UART
MIDI Interrupt Game Port Timer
FIFO
TXD
OPTiFM
16-bit Sigma-Delta Codec/Mixer CD-ROM Interface Volume Control
CA[2:0] IDECS1# IDECS3# CDOE# CDHOE# XIOR# XIOW# RESET# IDEIRQ MODEMINT
I2S Serial Audio Port
Modem Interface MODEMCS#
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82C931
Figure 2-2 Data Flow Block Diagram
Note:
There are four signals which are referenced by acronyms to make connections within the block diagram. HCO = Host Capture Output HPO = Host Playback Output FMO = FM Output SI = Serial In SO = Serial Out
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82C931
3.0
3.1
Signal Definitions
Mode Selection
Some pins of the 82C931 take on different functions depending upon its configured mode. The following subsections give the pin assignment and definitions for both the 931-MB and 931-AD modes, respectively. In addition to mode defined pins, the 82C931 has multiplexed pins. These pins are denoted with a plus (+) sign between signal names. Their definitions can also be found in the signal description tables. Table 3-3 defines abbreviated terms that are used throughout this section.
The 82C931 can be configured into two different modes: * 931-MB Mode - Single-chip motherboard application with 16-bit DMA support to enhance telephony-audio application performance. * 931-AD Mode - Single chip adaptor card with support for IDE CD-ROM and modem interfaces. Pins 11 is used to select the desired mode of the 82C931 (as shown in Table 3-1). Table 3-2 details the features in both of these modes.
Table 3-3
Mnemonic
Signal Definitions Legend
Description Analog-level compatible CMOS-level compatible External Ground Input Internal Input/Output Multiplexer Output Open drain Power Pull-down resistor Pull-up resistor Schmitt-trigger Tristate TTL-level compatible
Table 3-1
Mode Selection
Pin 11 1 0 Mode 931-MB 931-AD
Analog CMOS Ext G I Int
Table 3-2
Feature
Mode Features
931-MB No No No Yes(2) Yes(3) Yes Yes 931-AD(4) Yes Yes Yes(1) Yes(2) Yes Yes No
I/O Mux O OD P PD PU Smt TS TTL
IDE CD Interface IDE Interrupt Redirect Modem Interface Volume Control Serial Audio Port Internal OPTiFM 16-Bit DMA 1. 2. 3. 4.
Pins are shared between second Game Port and Modem interface. Volume Control can be used when second Game Port is not used by others. Pins are shared between second Game Port and Serial Audio port. The IDE and modem resources are programmable in 931-AD mode (available in 931 silicon revision 1.1 only).
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82C931
3.2 931-MB Mode
931-MB Mode PQFP Pin Diagram*
CDR LINER MICR MICL LINEL CDL AUXL OUTR OUTL MIXOUTL CINL MIXOUTR CINR AVCC VREF2 AGND RESET SA11 SA10 SA9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Figure 3-1
AUXR VREF1 AVCC AGND AGND AVCC OSCI OSCO RXD TXD GPIO1+MODE0 ROMCS+PNPEN SD15 SD14 SD13 SD12 GND VCC SD11 SD10 SD9 SD8 GD0 GD1 GD2+FSYNC GD3+SCLK GND GD4+VOLDN GD5+VOLUP GD6+SADO+VOLDWN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
82C931 931-MB Mode
SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SD7 SD6 SD5 SD4 VCC GND SD3 SD2 SD1 SD0 DRQ3 DRQ1 DRQ0 VCC GND IRQ9 IRQ7 IRQ5 IRQ10 IRQ11 AEN
* Pinout for TQFP Package is identical to pinout for PQFP Package.
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GD7+SADI+VOLUP DRQ5 DRQ6 RESET# GPIO2+ROMCLK GPIO3+ROMDOUT ROMDIN SA15 SA14 GND SA13 SA12 GPIO0+SDHOE+EXTROM# DACK5# DACK6# DACK0# DACK1# DACK3# IOW# IOR#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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82C931
Table 3-4
Pin No. Pin Name 1 AUXR 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VREF1 AVCC AGND AGND AVCC OSCI OSCO RXD TXD GPIO1+MODE0 ROMCS+PNPEN SD15 SD14 SD13 SD12 GND VCC SD11 SD10 SD9 SD8 GD0 GD1 GD2+FSYNC
931-MB Mode Numerical Pin Cross-Reference List
Pin Type I O P G G P I O I O I/O I/O I/O I/O I/O I/O G P I/O I/O I/O I/O I/O I/O I/O Pin No. Pin Name 26 GD3+SCLK 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Type I/O Pin No. Pin Name 51 AEN 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 IRQ11 IRQ10 IRQ5 IRQ7 IRQ9 GND VCC DRQ0 DRQ1 DRQ3 SD0 SD1 SD2 SD3 GND VCC SD4 SD5 SD6 SD7 SA0 SA1 SA2 SA3 Pin Type I I/O I/O I/O I/O I/O G P O-TS O-TS O-TS I/O I/O I/O I/O G P I/O I/O I/O I/O I I I I Pin No. Pin Name 76 SA4 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SA5 SA6 SA7 SA8 SA9 SA10 SA11 RESET AGND VREF2 AVCC CINR MIXOUTR CINL MIXOUTL OUTL OUTR AUXL CDL LINEL MICL MICR LINER CDR Pin Type I I I I I I I I I G O P I O I O O O I I I I I I I
GND G GD4+VOLDN I/O GD5+VOLUP I/O GD6+SADO+VOLDWN I/O GD7+SADI+VOLUP I/O DRQ5 O-TS DRQ6 O-TS RESET# O GPIO2+ROMCLK GPIO3+ROMDOUT ROMDIN SA15 SA14 GND SA13 SA12 I/O I/O I/O I I G I I I/O I I I I I I I
43 GPIO0+SDHOE +EXTROM# 44 DACK5# 45 DACK6# 46 DACK0# 47 DACK1# 48 DACK3# 49 IOW# 50 IOR#
Table 3-5
Pin Name AEN AGND AGND AGND AUXL AUXR AVCC AVCC AVCC CDL CDR CINL CINR DACK0# DACK1# DACK3# DACK5# DACK6# DRQ0 DRQ1 DRQ3 DRQ5 DRQ6 GD0 GD1
931-MB Mode Alphabetical Pin Cross-Reference List
Pin No. 51 4 5 85 94 1 3 6 87 95 100 90 88 Pin Type I G G G I I P P P I I I I Pin Name GD2+FSYNC GD3+SCLK GD4+VOLDN GD5+VOLUP GD6+SADO+VOLDWN GD7+SADI+VOLUP GND GND GND GND GND GPIO0+SDHOE +EXTROM# GPIO1+MODE0 GPIO2+ROMCLK GPIO3+ROMDOUT IOW# IOR# IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 LINEL LINER MICL Pin No. 25 26 28 29 30 31 17 27 40 57 66 43 11 35 36 49 50 54 55 56 53 52 96 99 97 Pin Type I/O I/O I/O I/O I/O I/O G G G G G I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I I I Pin Name MICR MIXOUTL MIXOUTR OSCI OSCO OUTL OUTR RESET RESET# ROMCS+PNPEN ROMDIN RXD SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 Pin No. 98 91 89 7 8 92 93 84 34 12 37 9 72 73 74 75 76 77 78 79 80 81 82 83 42 Pin Type I O O I O O O I O I/O I/O I I I I I I I I I I I I I I Pin Name SA13 SA14 SA15 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 TXD VCC VCC VCC VREF1 VREF2 Pin No. 41 39 38 62 63 64 65 68 69 70 71 22 21 20 19 16 15 14 13 10 18 58 67 2 86 Pin Type I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O P P P O O
46 I 47 I 48 I 44 I 45 I 59 O-TS 60 O-TS 61 O-TS 32 O-TS 33 O-TS 23 I/O 24 I/O
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3.2.1
3.2.1.1
931-MB Mode Signal Descriptions
ISA Bus Interface Signals Signal/Pin Type (Drive) I-TTL-Smt, 50K PU I-TTL-Smt, 50K PU I-TTL-Smt I-TTL-Smt, 50K PD I-TTL I/O-TTL (12mA) I/O-TTL (16mA) I-TTL, 50K PU O-TS (12mA), 50K PD I-TTL O-TS (12mA) OD-I/O-TTL (12mA)
Signal Name IOW# IOR# AEN RESET SA[15:0] SD[15:8] SD[7:0] DACK0# DACK1# DACK3# DRQ0 DRQ1 DRQ3 DACK5# DACK6# DRQ5 DRQ6 IRQ5 IRQ7 IRQ9 IRQ10 IRQ11
Pin No. 49 50 51 84 38, 39, 41, 42, 83:72 13:16, 19:22 71:68, 65:62 46 47 48 59 60 61 44 45 32 33 54 55 56 53 52
Signal Description
I/O Write Command I/O Read Command DMA Address Enable System Reset Input System Address Bus Lines 15 through 0 System Data Bus Lines 15 through 8 System Data Bus Lines 7 through 0 8-Bit DMA Acknowledge Bits 0, 1, and 3
8-Bit DMA Request Bits 0, 1, and 3
16-Bit DMA Acknowledge Bits 5 and 6 16-Bit DMA Request Bits 5 and 6 Interrupt Request Bits 5, 7, and 9 through 11: IRQ7 and IRQ9-11 are bidirectional for WSS auto interrupt determination.
3.2.1.2
MIDI Interface Signals Signal/Pin Type (Drive) I-TTL-Smt O (20mA)
Signal Name RXD TXD
Pin No. 9 10
Signal Description
Receive Data from 32KBaud MIDI UART Port Transmit Data to 32KBaud MIDI UART Port
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82C931
931-MB Mode Signal Descriptions (cont.)
3.2.1.3 Configuration and External PnP EEPROM Interface Signals Signal/Pin Type (Drive) I/O-TTL, PU (8mA)
Signal Name ROMCS PNPEN
Pin No. 12
Signal Description
External Serial EEPROM Chip Select PNP Mode Enable Jumper Input: Jumper setting is latched at reset power-on reset. This pin has an internal pull-up. Jumper pull-up: enable (default), pull-down: disable General Purpose Input/Output 931 Mode Configuration Bit 0: This pin is used to configure the 82C931 in either the 931-MB or 931-AD mode (refer to Table 3-1). These settings are latched into the 82C931 at reset. General Purpose Input/Output External Serial EEPROM Clock General Purpose Input/Output External Serial EEPROM Data Out External Serial EEPROM Data In EEPROM enable jumper input function is removed Buffered Reset (active low) General Purpose I/O Bit 0 SD[15:8] Buffer Output Enable: Set MCIR19[7] = 1 to enable SDHOE function on this pin. External EEPROM enable jumper input: jumper setting is latched at power-on reset. This pin has internal pull-up. Jumper pull-up: disable (default), pull-down: enable
GPIO1 MODE0
11
I/O-TTL, PU (8mA)
GPIO2 ROMCLK GPIO3 ROMDOUT ROMDIN RESET# GPIO0 SDHOE EXTROM
35
I/O-TTL, PD (12mA) I/O-TTL, PU (12mA) I/O-TTL, PD (12mA) O (12mA) I/O-TTL, PU (8mA)
36
37 34 43
3.2.1.4
Game Port and Serial Audio Interface Signals Signal/Pin Type (Drive) I/O-CMOS-Smt (8mA)
Signal Name GD7 SADI VOLUP GD6 SADO VOLDWN GD5 VOLUP
Pin No. 31
Signal Description
Game Port 2 Data Line 7 Serial Audio Data Input Volume Up: Interface for push-button volume control. Used to increase volume. An external pull-up is required on this pin.
30
I/O-CMOS-Smt (16mA)
Game Port 2 Data Line 6 Serial Audio Data Output Volume Down: Interface for push-button volume control. Used to decrease volume. An external pull-up is required on this pin.
29
I/O-CMOS (8mA)
Game Port 1 Data Line 5 An External pull-up is required on this pin. Volume Up: Interface for push-button volume control. Used to increase volume. VOLUP on pin 29 is only available in rev. 1.1 silicon.
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931-MB Mode Signal Descriptions (cont.)
3.2.1.4 Game Port and Serial Audio Interface Signals Signal/Pin Type (Drive) I/O-CMOS (8mA)
Signal Name GD4 VOLDN GD3 SCLK GD2 FSYNC GD1 GD0
Pin No. 28
Signal Description
Game Port 1 Data Line 4 An External pull-up is required on this pin. Volume Down: Interface for push-button volume control. Used to decrease volume. VOLDN on pin 28 is only available in rev. 1.1 silicon.
26
I/O-CMOS (8mA) I/O-CMOS (8mA) I/O-CMOS (8mA) I/O-CMOS (8mA)
Game Port 2 Data Line 3 Serial Audio Clock Game Port 2 Data Line 2 Serial Audio Synchronization Game Port 1 Data Line 1 Game Port 1 Data Line 0
25
24 23
3.2.1.5
Codec/Mixer Interface Signals Signal/Pin Type (Drive) I-Analog I-Analog I-Analog I-Analog I-Analog I-Analog I-Analog I-Analog O-Analog O-Analog O-Analog O-Analog I-Analog I-Analog O-Analog O-Analog
Signal Name MICL MICR LINEL LINER CDL CDR AUXL AUXR OUTL OUTR MIXOUTL MIXOUTR CINL CINR VREF1 VREF2
Pin No. 97 98 96 99 95 100 94 1 92 93 91 89 90 88 2 86
Signal Description
Microphone Input Left Microphone Input Right Line Input Left Line Input Right CD Input Left CD Input Right Auxiliary Input Left Auxiliary Input Right Output Left Output Right Mixer Output Left Mixer Output Right ADC Filter Pin Left ADC Filter Pin Right Analog Common: Normally connected to AGND with a 0.1F ceramic capacitor in parallel with a 10F electrolytic capacitor. Voltage Reference: Nominal 1.85V reference available externally. Not meant for current sourcing or sinking. Normally connected to AGND with a 0.1F ceramic capacitor in parallel with a 10F electrolytic capacitor.
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931-MB Mode Signal Descriptions (cont.)
3.2.1.5 Codec/Mixer Interface Signals Signal/Pin Type (Drive) I-Analog O-Analog
Signal Name OSCI OSCO
Pin No. 7 8
Signal Description
Oscillator Input: A 14.318MHz crystal oscillator is to be connected across this pin and the OSCO pin. Oscillator Output: See OSCI.
3.2.1.6
Power and Ground Pins Signal/Pin Type (Drive) P G P G
Signal Name VCC GND AVCC AGND
Pin No. 18, 58, 67 17, 27, 40, 57, 66 3, 6, 87 4, 5, 85
Signal Description
Power Connection Ground Connection Analog Power Connection Analog Ground Connection
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3.3 931-AD Mode
931-AD Mode PQFP Pin Diagram*
CDR LINER MICR MICL LINEL CDL AUXL OUTR OUTL MIXOUTL CINL MIXOUTR CINR AVCC VREF2 AGND RESET SA11 SA10 SA9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Figure 3-2
AUXR VREF1 AVCC AGND AGND AVCC OSCI OSCO RXD TXD GPIO1+MODE0 ROMCS+PNPEN SA15 SA14 SA13 SA12 GND VCC SADI SADO SCLK FSYNC GD0 GD1 GD2+IRQ3 GD3+IRQ4 GND GD4+VOLDN GD5+VOLUP GD6+MODEMINT+VOLDWN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
82C931 931-AD Mode
SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SD7 SD6 SD5 SD4 VCC GND SD3 SD2 SD1 SD0 DRQ3 DRQ1 DRQ0 VCC GND IRQ9 IRQ7 IRQ5 IRQ10 IRQ11 AEN
* Pinout for TQFP Package is identical to pinout for PQFP Package.
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GD7+MODEMCS#+ MODEM#+VOLUP XIOR# XIOW# RESET# CA2+ROMCLK+IDEDIS# CA1+ROMDOUT CA0+ROMDIN IDECS1# IDECS3# GND IDEIRQ+GPIO2 IRQ15+GPIO3 GPIO0+EXTROM# CDOE# CDHOE# DACK0# DACK1# DACK3# IOW# IOR#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Table 3-6
Pin No. Pin Name
931-AD Mode Numerical Pin Cross-Reference List
Pin Type I O P G G P I O I O I/O I/O I/O I/O I/O I/O G P I O I/O I/O I/O I/O I/O I/O Pin No. Pin Name Pin Type G I/O I/O I/O I/O O O O I/O I/O I/O O O G I/O I/O I/O O O I I I I Pin No. Pin Name Pin Type I I I/O I/O I/O I/O I/O G P O-TS O-TS O-TS I/O I/O I/O I/O G P I/O I/O I/O I/O I/O I/O I/O I/O Pin No. Pin Name Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I G O P I O I O O O I I I I I I I
1 AUXR 2 VREF1 3 AVCC 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AGND AGND AVCC OSCI OSCO RXD TXD GPIO1+MODE0 ROMCS+PNPEN SA15 SA14 SA13 SA12 GND VCC SADI SADO SCLK FSYNC GD0 GD1 GD2+IRQ3 GD3+IRQ4
27 GND 28 GD4+VOLDN 29 GD5+VOLUP 30 GD6+MODEMINT+ VOLDWN 31 GD7+MODEMCS#+ +MODEM#+VOLUP 32 XIOR# 33 XIOW# 34 RESET# 35 CA2+ROMCLK+ IDEDIS# 36 CA1+ROMDOUT 37 CA0+ROMDIN 38 39 40 41 42 43 44 45 46 47 48 49 IDECS1# IDECS3# GND IDEIRQ+GPIO2 IRQ15+GPIO3 GPIO0+EXTROM# CDOE# CDHOE# DACK0# DACK1# DACK3# IOW#
50 IOR# 51 AEN 52 IRQ11 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 IRQ10 IRQ5 IRQ7 IRQ9 GND VCC DRQ0 DRQ1 DRQ3 SD0 SD1 SD2 SD3 GND VCC SD4 SD5 SD6 SD7 SA0 SA1 SA2 SA3
76 SA4 77 SA5 78 SA6 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SA7 SA8 SA9 SA10 SA11 RESET AGND VREF2 AVCC CINR MIXOUTR CINL MIXOUTL OUTL OUTR AUXL CDL LINEL MICL MICR LINER CDR
Table 3-7
Pin Name AEN AGND AGND AGND AUXL AUXR AVCC AVCC AVCC CA0+ROMDIN CA1+ROMDOUT CA2+ROMCLK+ IDEDIS# CDHOE# CDL CDOE# CDR CINL CINR DACK0# DACK1# DACK3# DRQ0 DRQ1 DRQ3 FSYNC
931-AD Mode Alphabetical Pin Cross-Reference List
Pin No. 51 4 5 85 94 1 3 6 87 37 36 35 45 95 44 100 Pin Type I G G G I I P P P I/O I/O I/O O I O I Pin Name GD0 GD1 GD2+IRQ3 GD3+IRQ4 GD4+VOLDN GD5+VOLUP GD6+MODEMINT +VOLDWN GD7+MODEMCS#+ +MODEM#+VOLUP GND GND GND GND GND GPIO0+EXTROM# GPIO1+MODE0 IDECS1# IDECS3# IDEIRQ+GPIO2 IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 IRQ15+GPIO3 Pin No. 23 24 25 26 28 29 30 31 17 27 40 57 66 43 11 38 39 41 54 55 56 53 52 42 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O G G G G G I/O I/O O O I/O I/O I/O I/O I/O I/O I/O Pin Name IOR# IOW# LINEL LINER MICL MICR MIXOUTL MIXOUTR OSCI OSCO OUTL OUTR RESET RESET# ROMCS+PNPEN RXD SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 Pin No. 50 49 96 99 97 98 91 89 7 8 92 93 84 34 12 9 72 73 74 75 76 77 78 79 80 81 Pin Type I I I I I I O O I O O O I O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Name SA10 SA11 SA12 SA13 SA14 SA15 SADI SADO SCLK SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 TXD VCC VCC VCC VREF1 VREF2 XIOR# XIOW# Pin No. 82 83 16 15 14 13 19 20 21 62 63 64 65 68 69 70 71 10 58 18 67 2 86 32 33 Pin Type I/O I/O I/O I/O I/O I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O O P P P O O O O
90 I 88 I 46 I 47 I 48 I 59 O-TS 60 O-TS 61 O-TS 22 I/O
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3.3.1
3.3.1.1
931-AD Mode Signal Descriptions
ISA Bus Signals Signal/Pin Type (Drive) I-TTL-Smt 50K PU I-TTL-Smt 50K PU I-TTL-Smt I-TTL-Smt 50K PD I/O-TTL (12mA) I/O-TTL (16mA) I-TTL 50K PU
Signal Name IOW# IOR# AEN RESET SA[15:0] SD[7:0] DACK0# DACK1# DACK3# DRQ0 DRQ1 DRQ3 GPIO0 EXTROM# IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 IRQ15 GPIO3
Pin No. 49 50 51 84 13:16, 83:72 71:68, 65:62 46, 47, 48 59 60 61 43
Signal Description
I/O Write Command I/O Read Command DMA Address Enable System Reset Input System Address Bus Lines 15 through 0 System Data Bus Lines 7 through 0 DMA Acknowledge Bits 0, 1, and 3
O-TS, 50K PD DMA Request Bits 0, 1, and 3 (12mA) I/O-TTL, PU (8mA)
General Purpose I/O Bit 0 External EEPROM Enable Jumper Input: Jumper setting is latched at reset time. (If pin 43 is pulled up, external EEPROM is enabled.) Interrupt Request Bits 5, 7, and 9 through 11: IRQ7 and IRQ[9:11] are bidirectional for WSS auto interrupt determination
54 55 56 53 52 42
OD, I/O-TTL (12mA)
I/O-TTL (12mA)
Interrupt Request Bit 15 General Purpose I/O Bit 1
3.3.1.2
MIDI Interface Signals Signal/Pin Type (Drive) I-TTL-Smt O (20mA)
Signal Name RXD TXD
Pin No. 9 10
Signal Description
Receive Data from 32KBaud MIDI UART Port Transmit Data to 32KBaud MIDI UART Port
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931-AD Mode Signal Descriptions (cont.)
3.3.1.3 Configuration, External PnP EEPROM, and IDE CD-ROM Interface Signals Signal/Pin Type (Drive) I/O-TTL, PU (8mA)
Signal Name ROMCS PNPEN
Pin No. 12
Signal Description
External Serial EEPROM Chip Select PNP Mode Enable Jumper Input: Jumper setting is latched at poweron reset. This pin has an internal pull-up. Jumper pull-up: enable (default), pull-down: disable. General Purpose I/O Bit 1 931 Mode Configuration Bit 0: This pin is used to configure the 82C931 in either the 931-MB or 931-AD mode (refer to Table 3-1). These settings are latched into the 82C931 at reset. IDE CA2: Buffered SA2 for CD-ROM External Serial EEPROM Clock IDE Disable: Jumper selection to disable IDE resource. No connect equals IDE enabled. Pull down equals IDE disabled. (Available in revision 1.1 silicon only.)
GPIO1 MODE0
11
I/O-TTL, PU (8mA)
CA2 ROMCLK IDEDIS#
35
I/O-TTL, PD (12mA)
CA1 ROMDOUT CA0 ROMDIN IDECS1# IDECS3# IDEIRQ GPIO2 RESET# CDOE# CDHOE# XIOR# XIOW#
36
I/O-TTL, PD (12mA) I/O-TTL, PD (12mA) O-TTL (12mA) O-TTL (12mA) I/O-TTL (12mA)
IDE CA1: Buffered SA1 for CD-ROM. External Serial EEPROM Data Out IDE CA0: Buffered SA0 for CD-ROM. External Serial EEPROM Data In IDE CD-ROM Chip Select Bit 1: CD-ROM chip select for address decode range 0170h through 0177h. IDE CD-ROM Chip Select Bit 3: CD-ROM chip select for ISA address decode range 0376h through 0377h. IDE CD-ROM Interrupt: Interrupt input from IDE CD-ROM which redirect to IRQ5, 7, 9, 10, 11, 15 according to PNP logic. General Purpose I/O Bit 2
37
38 39 41
34 44 45 32 33
O (12mA) O-TTL (8mA) O-TTL (8mA) O-TTL (12mA) O-TTL (12mA)
Buffered Reset (active low) CD Output Enable: Enables low-order [7:0] of the CD data buffer. CD High Output Enable: Enables high-order [15:8] of CD data buffer. IDE Buffered IOR# IDE Buffered IOW#
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931-AD Mode Signal Descriptions (cont.)
3.3.1.4 Game Port and Modem Interface Signals Signal Type (Drive) I/O-CMOS-Smt (8mA)
Signal Name GD7 MODEMCS# MODEM#
Pin No. 31
Signal Description
Game Port 2 Data Line 7 Modem Chip Select: Output to external modem chip select pin. Modem Interface Enable Jumper Input: Jumper setting is latched at power-on reset. Jumper pull-up: disable (default), pull-down: enable. An external pull-up is required on this pin. Volume Up: Interface for push-button volume control. Used to increase volume.
VOLUP GD6 MODEMINT VOLDWN GD5 VOLUP GD4 VOLDN GD3 IRQ4 GD2 IRQ3 GD1 GD0 24 23 25 26 I/O-CMOS (8mA) I/O-CMOS (8mA) I/O-CMOS (8mA) I/O-CMOS (8mA) 28 I/O-CMOS (8mA) 29 I/O-CMOS (8mA) 30 I/O-CMOS-Smt (8mA)
Game Port 2 Data Line 6 Modem Interrupt: Interrupt signal from external modem. Volume Down: Interface for push-button volume control. Used to decrease volume. An external pull-up is required on this pin. Game Port 1 Data Line 5 An external pull-up is required on this pin. Volume Up: Interface for push-button volume control. Used to increase volume. VOLUP on pin 29 is only available in rev. 1.1 silicon. Game Port 1 Data Line 4 An external pull-up is required on this pin. Volume Down: Interface for push-button volume control. Used to decrease volume. VOLDN on pin 28 is only available in rev. 1.1 silicon. Game Port 2 Data Line 3 Interrupt Request Bit 4 Game Port 2 Data Line 2 Interrupt Request Bit 3 Game Port 1 Data Line 1 Game Port 1 Data Line 0
3.3.1.5
Codec/Mixer Interface Signals Signal/Pin Type (Drive) I-Analog I-Analog I-Analog I-Analog I-Analog I-Analog
Signal Name MICL MICR LINEL LINER CDL CDR
Pin No. 97 98 96 99 95 100
Signal Description
Microphone Input Left Microphone Input Right Line Input Left Line Input Right CD Input Left CD Input Right
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931-AD Mode Signal Descriptions (cont.)
3.3.1.5 Codec/Mixer Interface Signals (cont.) Signal/Pin Type (Drive) I-Analog I-Analog O-Analog O-Analog O-Analog O-Analog I-Analog I-Analog O-Analog O-Analog
Signal Name AUXL AUXR OUTL OUTR MIXOUTL MIXOUTR CINL CINR VREF1 VREF2
Pin No. 94 1 92 93 91 89 90 88 2 86
Signal Description
Auxiliary Input Left Auxiliary Input Right Output Left
Output Right
Mixer Output Left Mixer Output Right ADC Filter Pin Left ADC Filter Pin Right Analog Common: Normally connected to AGND with a 0.1F ceramic capacitor in parallel with a 10F electrolytic capacitor. Voltage Reference: Nominal 1.85V reference available externally. Not meant for current sourcing or sinking. Normally connected to AVS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic capacitor. Oscillator Input: A 14.318MHz crystal oscillator is to be connected across this pin and the OSCO pin. Oscillator Output: See OSCI.
OSCI OSCO
7 8
I-Analog O-Analog
3.3.1.6
Serial Audio Interface Signals Signal/Pin Type (Drive) I-TTL O-TTL I/O-TTL I/O-TTL
Signal Name SADI SADO SCLK FSYNC
Pin No. 19 20 21 22
Signal Description
Serial Audio Data Input Serial Audio Data Output Serial Audio Clock Serial Audio Synchronization
3.3.1.7
Power and Ground Pins Signal/Pin Type (Drive) P G P G
Signal Name VCC GND AVCC AGND
Pin No. 18, 58, 67 17, 27, 40, 57, 66 3, 6, 87 4, 5, 85
Signal Description
Power Connection Ground Connection Analog Power Connection Analog Ground Connection
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4.0 Functional Description
A PnP configuration sequence is carried out by either the system BIOS supporting PnP or Configuration Manager software of the operating system. It is used to map the various functional blocks (logical devices) within the 82C931 into the host system address space as well as to configure the DMA and IRQ channels. The configuration sequence occurs as follows: 1. 2. 3. The 82C931 is isolated from the system. A unique indentifier (handle) is programmed into the 82C931 and the resource data is read. After the resource requirement and capabilities are determined, the handle is used to assign conflict-free resources by programming the appropriate information into the 82C931 configuration registers a logical device at a time After the configuration registers are programmed, the 82C931 leaves the configuration mode and each logical device is activated individually. The bus interface of each logical device is then enabled.
The 82C931 is an optimized single chip solution with built-in Plug-and-Play functions, built-in FM synthesizer and 16-bit Sigma-Delta Codec to provide all of the features needed to create the following sound characteristics and applications: * 16-bit sound quality Sound Blaster Pro and Windows Sound System compatible card * 22 voice FM synthesis * 16-bit CD-quality digital wave audio up to 44.1KHz stereo * Game port * MPU-401 MIDI interface * Wavetable synthesis upgrade The following sub-sections will discuss these built-in functions in detail.
4.
4.1
Plug and Play
The OPTi 82C931 supports the ISA Plug and Play (PnP) Specification 1.0a. After power-up, the 82C931 is isolated from other PnP cards in the host system by the system software. With this mechanism, the I/O address, IRQ and DMA usage of the 82C931 can be configured by the system according to the free resources available. As a result, the chance of getting a resource conflict is minimized. The PnP function is disabled by pulling pin 12 (PNPEN) of the 82C931 low at power-up; otherwise the 82C931 will operate in PnP mode.
The 82C931 supports the following logical devices: * IDE CD-ROM interface * Windows Sound System * FM synthesis * Sound Blaster Pro * Game Port * MPU-401 MIDI interface * Modem interface * 82C931 Master Control
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82C931
4.2
4.2.1
16-Bit Codec/Mixer
Codec
* L/R - to select between the left and right channels for both the ADC and DAC data. * MCLK - This internal master clock signal is synthesized by the frequency synthesizer from the crystal reference of 14.318MHz. One of 236 frequencies may be selected through the 8-bit FSEL line. MCLK is not active when the frequency synthesizer is powered down. The frequency of MCLK is 256 times the sampling frequency. The DAC left/right 16-bit input data are multiplexed onto DAC[15:0] and fed into the codec. The L/R signal qualifies the data. The period of L/R is equal to that of the codec sampling frequency. One set of left/right 16-bit input data to the DAC is sent every L/R cycle. When L/R is low, the data on DAC[15:0] is meant for the left channel; when L/R is high, the data is meant for the right channel. This means that the DAC treats data packets L1 and R1 as belonging to the same sampling instance; while L2 and R2 are data for the next sampling instance. The ADC left/right 16-bit output data are similarly multiplexed onto the ADC[15:0] bus.
Features of the built-in 16-bit stereo sigma-delta codec include: * Sigma-delta stereo ADC with 128X over-sampling * Sigma-delta stereo DAC with 128X over-sampling * On-chip 8X Interpolation Filter * On-chip analog post filter * Single-ended input and output * Sampling rate of 5KHz to 48KHz The codec serial interface provides a means to read and write 16-bit stereo data from the ADC or to the DAC respectively. The interface (as shown in Figure 4-1) consists of the following lines: * DAC[15:0] - to write to the DAC 16-bit input * ADC[15:0] - to read the ADC 16-bit output
Figure 4-1
Functional Block Diagram
AVCC AGND CINR
Stereo 16-Bit Sigma-Delta ADC Analog Sigma-Delta Modulator Analog Sigma-Delta Modulator 128:1 Decimation Filter 128:1 Decimation Filter 16 fs 16 fs Serial Interface
1 128fs 1 128fs
CINL
Stereo 16-Bit Sigma-Delta DAC DACL Analog Low-Pass Filter Analog Low-Pass Filter Digital Sigma-Delta Modulator Digital Sigma-Delta Modulator 16 8fs 16 8fs 8X Interpolator
DACR
8X Interpolator
VREF MCLK
Voltage Reference Clock Generation
Power Supply
VCC VCC
PD
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4.2.2 Mixer
The built-in mixer mixes two mono microphone level inputs (MICL/R) and five stereo analog line level input sources (LINEL/R, CDL/R, AUXL/R, FML/R, and DACL/R) with individual mixer programmable gain and mute control. The DACL/R stereo analog inputs are routed to a programmable circuit with 1.5dB steps (total of 32 levels). Internal amplifiers with a programmable 20dB gain block are provided for the MIC input (only). The remaining stereo analog inputs are routed to a programmable gain circuit which can be programmed in 3dB steps (total of 16 levels). Also, internal amplifiers with a programmable 20dB gain block are provided. Level changes only take effect on zero crossings to minimize audible artifacts. AC coupling is mandatory for these inputs since any DC offset on the input will be amplified. MIXOUTL (mixer record output left) must be connected to CINL (codec analog input left) with a ceramic capacitor. MIXOUTR (mixer record output right) must be connected to CINR (codec analog input right) with a ceramic capacitor. MIXOUT/R are routed via gain control (1.5dB steps: total of 16 levels). Analog output OUTL/R are routed via a master volume control which provides 0db to 94.5db of attenuation, adjustable in 3dB steps. The Codec Indirect Registers used for programming the various functions/gain levels for the mixer. For details regarding these registers, refer to Table 510 and Table 5-11 in the Register Section. Figure 4-2 shows a functional block diagram of the mixer.
Figure 4-2
Mixer Block Diagram
2 2 2
+20dB
2
Mux
Gain (16 Levels) 0 to 22.5dB (1.5dB step)
2
MIXOUTL/R
16 Levels -33 to 12dB (3dB steps) 2 2
2
MICL/R
ATTEN + MUTE
2
2
LINEL/R
ATTEN + MUTE
2
2
CDL/R
ATTEN + MUTE
2
2
2
AUXL/R
ATTEN + MUTE
2
Zero Cross Detect
Master Volume ATTEN/MUTE (32 Levels) 0 to -93dB (3dB steps)
2
OUTL/R
2
FML/R
ATTEN + MUTE
2
2
DACL/R
ATTEN + MUTE 32 Levels 0 to -46.5dB (1.5dB step)
2 Mixer Latch Control
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4.3 Frequency Synthesizer
Table 4-1 gives the Frequency Selection, where the FSEL[7:0] address is given in decimal equivalent. FOUTactual is the FS output frequency for a given FSEL code and %error gives the difference between the FOUT-actual and the target FOUT-spec. Shaded table entries refer to the 14 critical sampling frequencies. The error for these frequencies fall within 0.15%. The Frequency Synthesizer (FS) block generates the codec sampling clock from a reference crystal oscillator of 14.318MHz. The output frequency of the FA is equal to 256 times fs (where fs = codec sampling frequency). One of the 236 frequencies may be generated by the FS. The selection of the FS output frequency is done via programming eight register bits in the Digital Audio Processor Write Command/Data (40h/FSEL[7:0]).
Table 4-1
FSEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
FS Output Frequencies
FSEL 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 FOUT-actual (Hz) 4713.176 4716.962 4739.804 4759.973 4783.460 4806.457 4833.430 4847.240 4877.589 4906.113 4934.972 4955.795 4971.528 4993.722 5019.331 5049.208 5084.517 5115.520 5126.888 5151.419 5178.675 5202.762 5243.408 5268.739 5290.646 5326.637 5346.220 5377.855 5412.550 5437.608 5456.555 5493.094 5514.194 5519.377 5523.920 5592.969 5668.549 5680.359 5720.082 5746.201 5785.830 5804.024 5843.400 FSEL 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 FOUT-actual (Hz) 5887.335 5915.640 5949.967 5992.466 6023.197 6059.049 6101.420 6138.624 6168.715 6214.410 6260.786 6292.090 6331.663 6377.947 6408.610 6453.425 6491.839 6544.963 6579.963 6615.339 6670.513 6711.562 6750.135 6802.259 6848.533 6895.441 6935.281 6991.211 7049.961 7089.679 7139.960 7190.960 7250.145 7295.177 7359.169 7402.459 7457.292 7512.943 7573.812 7626.775 7690.332 7752.630 7813.706 FSEL 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 FOUT-actual (Hz) 7877.421 7935.969 7989.955 8066.782 8129.315 8196.592 8262.340 8329.953 8389.453 8474.195 8544.813 8636.202 8691.776 8773.284 8849.634 8924.950 9005.628 9088.574 9175.964 9219.179 9321.614 9433.923 9519.947 9599.872 9710.015 9805.854 9904.215 10025.133 10098.416 10209.387 10302.837 10418.275 10532.214 10634.518 10755.709 10875.217 10986.188 11028.389 11263.617 11360.718 11485.561 11616.166 11774.671 FSEL 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 FOUT-actual (Hz) 11910.952 12046.394 12189.804 12356.559 12494.931 12663.325 12817.220 12983.677 13159.926 13332.077 13511.104 13697.066 13866.865 14099.921 14286.387 14487.810 14703.165 14914.583 15147.624 15380.664 15627.413 15871.938 16018.697 16379.408 16665.917 16948.390 17244.987 17537.275 17839.642 18177.148 18511.939 18905.810 19225.830 19617.129 20034.515 20418.775 20836.550 21286.672 21750.434 22049.203 22721.435 23238.391 23821.904 FSEL 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 FOUT-actual (Hz) 24394.863 24989.860 25634.440 26303.566 27446.976 27703.490 28566.238 29417.563 30295.247 31254.825 32007.953 33080.364 34502.080 35691.971 37053.418 38003.505 40005.262 41693.039 44098.407 45495.044 48006.315
FOUT-actual (Hz) 3909.064 3924.890 3938.710 3947.978 3951.554 3957.289 3994.978 4030.968 4033.391 4047.543 4067.614 4084.752 4092.416 4112.477 4131.170 4142.940 4164.977 4178.655 4209.761 4221.108 4237.097 4255.520 4276.976 4302.284 4302.284 4327.892 4350.087 4369.507 4386.642 4415.502 4433.451 4448.952 4462.475 4488.185 4500.090 4523.725 4544.287 4565.689 4584.401 4601.810 4605.974 4609.590 4660.807
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4.4 16-Bit Type F DMA Playback
The 82C931 supports the Type F DMA playback. customer wants to use a different resource data and serial identifier to customize their application, an external EEPROM can be used. To use an external EEPROM, pin 43 (EXTROM#) must be pulled low. This enables the resource data and serial identifier to be read from the external EEPROM instead of the 82C931's internal storage. The 82C931 provides a serial EEPROM interface that is compatible with devices from a number of vendors. A 512- byte EEPROM is sufficient for information required by PnP. Pin 35 of the 82C931 provides the data clock for the EEPROM. Pin 36 provides data to the EEPROM, while pin 37 gets input from the EEPROM.
4.5
Modem Interface
The 82C931 includes the modem as a PnP logical device, as well as interface pins to connect to a modem chipset. When PnP is activated (931-AD Mode), the 82C931 provides the resource configuration for the modem chipset, such as the I/O address range and interrupt level. The modem interface pins include pin 31 (MODEMCS#), pin 30 (MODEMINT), pin 25 (IRQ3), and pin 26 (IRQ4). To use the modem interface, pin 31 (MODEM#) must be pulled low. If a modem is connected with the 82C931, the joystick port will provide support for one joystick only.
4.8
Serial Audio Interface
When the 82C931 is implemented in MB mode, the SAIO connector is coming from pins 25, 26, 30 and 31.
931-MB mode (no pull-down at pin#11) SCLK FSYNC (LRCLK) SADI SADO pin#26 pin#25 pin#31 pin#30 931-AD mode (pull-down at pin#11) pin#21 pin#22 pin#19 pin#20
4.6
Push Button Volume Control
In silicon revision 1.0, two pins of the joystick interface can be used as volume control push-buttons (pin 30 as volume down, and pin 31 as volume up) so that the speaker volume can be controlled through front panel buttons in desktop or notebook PCs. Appropriate software drivers are needed to enable this feature. When the volume control feature is enabled, only one joystick will be supported by the joystick port. In silicon revision 1.1, the volume pins are additionally available in pins 28 and 29, as shown: pin#31 & 29 pin#30 & 28 Volume up Volume down
The 82C931's serial audio interface supports the following formats: * I2S-justified format (ZV port) and its variations. * Sony format (short right-justified format, used by OPTi's wavetable chip and the Philips TDA1311AT DAC). * AT&T PCM codec T7525 compatible16-bit mono format. Please refer to sections 4.8.6, ZV-Port I2S, 4.8.7, Advanced Precision General Purpose Serial Port, 4.8.8, TDA1311 Stereo Continuous Calibration, for the respective timing diagrams.
These two pins are active-low, edge-triggering and pulled up internally. When the button is pressed and the corresponding pin is activated, the register bits MCIR16[5:4] are set accordingly. The software drivers poll these two bits periodically. The scheme is as follows:
Buttons Press UP button Press Down button Press both Up & Down button MCIR[5:4] (BUTUP:BUTDN) 10 01 11 Action required for the driver increase the volume by one step decrease the volume by one step mute
4.8.1
2
I2S-justified format and its variations
The register bits MCIR[5:4] will be cleared automatically after they are read by the driver.
4.7
External Serial EEPROM
In the I S-justified format (ZV-port), LRCLK is low for the left channel, and high for the right channel. The left-channel MSB is left-justified to the high-to-low LRCLK transition with a single SCLK delay. SDATA could be SADI when the 931 is in receive mode, and SADO when the 931 is in transmit mode. The LRCLK period is programmable with a minimum of 32 SCLKs (MC22[4]). The following example assumes LRCLK period is greater than 32 SCLKs. Please note that in ZV port, there is one more signal MCLK defined but this is not needed for the 931.
The 82C931 has the resource data and serial identifier required by the PnP specification stored internally. If an OEM
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To program the 931 in the I2S-justified mode, the MC22 and MC21 registers need to be set. The relevant MC22 and MC21 bit definitions are shown below for reference. I2S-justified mode (ZV-port): MC22[7:0] = "00110001" (31H). MC21[7:0] = "10000010" (82H). There are other I2S variations: left-justified and right-justified. For the left-justified, LRCLK is high for the left channel, and low for the right channel. The MSB is left-justified to an LRCLK transition, with zero SCLK delay. MC22[7:0] = "00110100" (34H). MC21[7:0] = "10000010" (82H). For the right-justified, LRCLK is high for the left channel, and low for the right channel. The MSB is delayed from an LRCLK transition, the LSB will be right-justified to the next LRCLK transition. MC22[7:0] = "00010100" (14H). MC21[7:0] = "10000010" (82H).
MC22[7:0] MC22[7:0]
could be used to save a T7525 as the voice codec in modem/audio combo solution. To program the 931 in T7525 mode: MC22[7:0] = "00110010" (32H) MC21[7:0] = "10000010" (82H) In short summary:
I2Sjustified 31H* leftjustified 34H* rightjustified 14H* 82H Sony format 04H* T7525 format 32H
* The MC22[4] bit setting may vary, depending on the LRCLK period (32 SCLK or more).
4.8.4
Testing I2S format (ZV port) with Audio Precision machine
The Audio Precision machine system two 2322 has a serial audio data port that can generate a test tone in the I2S format with programmable FSYNC, ranging from 24KHz to 48KHz. The 931 was tested with AP machine in various test tones: 256Hz, 1KHz and 3KHz in both sine wave and square wave with FSYNC = 48KHz. To test out the feature, the AP machine is hooked up with the 931 with appropriate connections (AP's pin#6, 12, 14 are SDATA, SCLK and FSYNC, respectively). The next step is to setup the MC22 to "31H" and MC21 to "82H". Then the test tone could be heard from the speaker connected to the 931. Please note that there might be some noise in the speaker. This is due to unshielded cable used to connect the serial audio interface. Shielding the cable would help improve the audio quality.
4.8.2
Sony format1
This data format is essentially the same as the I2S right-justified format. Normally there are only 32 SCLKs in a LRCLK period. The LRCLK is high for the left channel, and low for the right channel. The MSB comes in first. To set up the 931 in Sony format: MC22[7:0] = "00000100" (04H). MC21[7:0] = "10000010" (82H).
4.8.3
AT&T PCM codec T7525 compatible 16-bit mono format
The 931 supports the T7525 receive timing - word format with positive FSYNC. The benefit is that the 931's secondary DAC
4.8.5
Relevant MC register settings
Default: 00h bit 4 CLK32 bit 3 SCLK Polarity bit 2 FSYNC Polarity bit 1 Pulse Mode bit 0 I2S Mode
MC22 Serial Audio format control register (R/W) bit 7 Reset ASIO Bit 5 bit 6 ASIO test enable bit 5 First16-bit
First16-bit: Specifies where the data is located in the LRCLK period 0: data located at the last 16 bits of the left/right channel in an LRCLK period 1: data located at the first 16 (or 17) bit of the left/right channel in an LRCLK period CLK32: Specifies the number of SCLKs per LRCLK period, used only in delay-mode or pulse-mode ASIO 0: 32 SCLK per LRCLK period 1: more than 32 SCLK per LRCLK period
Bit 4
1.
Short right-justified format, used by OPTi's wavetable chip and the Philips TDA1311AT DAC.
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Bit 3 SCLK polarity: 0: SDATA and LRCLK change at the rising edge of SCLK 1: SDATA and LRCLK change at the falling edge of SCLK FSYNC (LRCLK) polarity: 0: LRCLK is LOW for the left channel, HIGH for the right channel 1: LRCLK is HIGH for the left channel, LOW for the right channel Pulse mode: Used for AT&T T7525 codec or CS8412 DSP data format 0: Pulse mode disabled 1: Pulse mode enabled, used for AT&T T7525 or CS8412 data format I2S mode: MSB delay mode 0: Zero SCLK delay from an LRCLK transition to MSB data 1: One SCLK delay from an LRCLK transition to MSB data Default: 00h bit 3 SPCDSEL bit 2 ADCSEL bit 1 FDACSEL bit 0 DACSEL
Bit 2
Bit 1
Bit 0
MC21 Serial Audio selection control register (R/W) bit 7 bit 6 bit 5 bit 4
CTL_SEL[1:0]
P2S_SEL[1:0]
bit [7:6] CTL_SEL[1:0]: ASIO shift clock selection 00/11: Use the shift clock from internal FS 01: Use FM timing 10: Use external SCLK bit 1 FDACSEL: selects the data source to the FDAC 0: FDAC takes FM data 1: FDAC takes SADI (if SPCDSEL=0) or second DMA playback data (if SPCDSEL=1)
4.8.6
ZV-Port I2S
4.8.6.2 SDATA This signal is the digital PCM signal that carries the audio information. Digital audio data is transferred using the I2S format. I2S Format The I2S format is shown below. The digital audio data is left channel-MSB justified to the high-to-low going edge of the LRCLK plus one SCLK delay.
4.8.6.1 LRCLK This signal determines which audio channel (left/right) is currently being input on the audio Serial Data input line. LRCLK is low to indicate the left channel and high to indicate the right channel. Typical frequency values for this signal are 48KHz, 44.1KHz, 32KHz, and 22KHz.
Figure 4-3
I2S Format
Left Channel
LRCLK SCLK SDATA
Right Channel
15 14 13 12 1110 9 8
76 5 4 3
2 1 0 15 14 13 12 1110 9 8
76 5 4 3
21 0
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4.8.6.3 SCLK This signal is the serial digital audio PCM clock. 4.8.6.4 MCLK This signal is the Master clock for the digital audio. MCLK is asynchronous to LRCLK, SDATA and SCLK. The MCLK must be either 256x or 384x the desired Input Word Rate (IWR). IWR is the frequency at which words for each channel are input to the DAC and is equal to the LRCLK frequency. The following table illustrates several standard audio word rates and the required MCLK and LRCLK frequencies. Typically, most devices operate with 384fx master clock. The ZV Port audio DAC should support an MCLK frequency of 384fs. This results in the frequencies shown below.
LRCLK (KHz) Sample Frequency 22 32 44.1 48 SCLK (MHz) 32xfs 0.704 1.0240 1.4112 1.5360 MCLK (MHz) 384x 8.448 12.2880 16.9344 18.4320 6 7 8 Serial Output Data (output) Ground Ground 14 15
4.8.7
Advanced Precision General Purpose Serial Port
The 15-pin "D-sub" connector on the rear panel provides all input and output signals for a general purpose serial input.output port, plus DSP-program specific input and output pins which may be used in certain DSP (.AZ2) programs. The pinout of the connector is detailed below. All inputs are TTL level compatible CMOS. All outputs are CMOS isolated by 50 series resistors and rise time limiting networks.
Pin 1 2 3 4 5 Function Ground +5V (tied to unused inputs high) Auxiliary Input (DSP program specific) Ground Ground Pin 9 10 11 12 13 Function Serial Input Master Clock (input) Serial Input Bit Clock (input) Auxiliary Output (DSP program specific) Serial Output Bit Clock (output) Serial Input Data (input) Serial Output Frame Sync (output) Serial Input Frame Sync (input)
Figure 4-4
General Purpose Serial Port, Timing Relationships
MSB LSB MSB LSB MSB LSB MSB MSB
Bit Clock In Data In Frame Sync In
CHAN A Channel A Channel B CHAN A
Detail
CLK 63 CLK 0 CLK 1 CLK 2
Detail
CLK 31 CLK 32 CLK 33 CLK 34
Bit Clock In
CH A MSB 3 4
Data In Frame Sync In
CH B MSB 3 4
1
2
1
2
1. 2. 3. 4.
FRAME SYNC INPUT SETUP TIME (from falling edge, las bit clock previous subframe) 30nS minimum FRAME SYNC INPUT SETUP TIME (to falling edge, first bit clock of present subframe) 30nS minimum DATA INPUT SETUP TIME (to bit clock falling edge) 30nS minimum DATA INPUT HOLD TIME (from bit clock falling edge) 45nS minimum
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4.8.8 TDA1311 Stereo Continuous Calibration Format of Input Signals
Figure 4-5
DATA
MSB
LSB
MSB
LSB
BCK
WS SAMPLE OUT
LEFT
RIGHT
MKA488
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5.0
5.1
Register Descriptions
I/O Base Addresses
Table 5-1
Base Register MCBase
Table 5-1 lists the I/O base address registers of the 82C931. These base addresses are programmable, which assists in avoiding possible I/O port conflicts among different devices. The configuration registers, called MC Indirect Registers, located via MCBase control most functions of the 82C931. An indirect addressing scheme is used to access the MC Indirect Registers. The MC address (0E0Eh-0EFEh) and data (0E0Fh-0FFFh) I/O port addresses are fully programmable. The only fixed I/O port used by the 82C931 is at 0F8Dh. The remaining I/O base address registers are accessed by the same type of indexing scheme as MCBase (CPU Direct I/O R/W). Table 5-2 gives the register map of the 82C931.
82C931 I/O Base Addresses
Function Configuration Digital Audio Processor Windows Sound System IDE CD ROM AdLib OPL4 MPU-401 Address Selections 0F8D; 0E0[E..F] to 0FF[E..F] 220/240 530/640/E80/F40 170/370 388 380 300/310/320/330
SBBase WSBase IDEBase ALBase OPL4Base MIDIBase
Table 5-2
I/O Address SBBase+00h (or ALBase+00h) SBBase+00h (or ALBase+00h) SBBase+01h (or ALBase+01h) SBBase+02h (or ALBase+02h) SBBase+03h (or ALBase+03h) SBBase+04h SBBase+05h SBBase+06h SBBase+08h SBBase+08h SBBase+09h SBBase+0Ah SBBase+0Ch SBBase+0Ch SBBase+0Eh WSBase+00h-03h WSBase+00h-03h WSBase+04h WSBase+05h WSBase+06h WSBase+07h 200h-201h 0F8Dh
82C931 Register Map
Register Name (Type) Left FM Status Port (RO) Left FM Register Address Port (WO) Left FM Data Port (WO) Right FM Register Address Port (WO) Right FM Data Port (WO) Mixer Address Port (WO) Mixer Data Port (R/W) DAP Reset (WO) FM Status Port (RO) FM Register Address Port (WO) FM Data Port (WO) DAP Read Data (RO) DAP Write Data/Cmd (WO) DAP Write Buffer Status (RO) DAP Output Buffer Status (RO) Configuration (WO) Version (RO) Codec Index Reg (R/W, exists in Codec and shadowed in 82C931) Codec Indexed Data Reg (R/W, exists in Codec only) Codec Status Reg (R/W, exists in Codec only) Codec Direct Data (R/W, exists in Codec only) Game Port (R/W) MCBase/Password Register - Specifies: MC Index Port Address (R/W) MC Data Port Address (R/W) OPL4 (R/W) OPL5 (R/W)
5.2
MCBase Register
MCBase is the Direct MC base address register which controls access to the MC Indirect Registers (MCIR1-23). MCIR1-23 control most of the basic functions of the 82C931 (i.e., CD-ROM select, base decode address select, etc.). To avoid possible conflict of I/O ports with different devices, the 82C931 uses a unique indirect addressing scheme with the base addresses being programmable. Under this design scheme, the only fixed I/O port used by 82C931 is at 0F8Dh. The MC address and data I/O port addresses are fully programmable, from 0E0Eh-0EFEh (address port) and 0E0Fh0FFFh (data port). To access the MC registers: (1) All MC registers in 82C931 are password protected. To read or write into the MC registers, the password E4h must be written into I/O Port 0F8Dh before accessing the address or data port. (2) The address and data access port address can be fully programmable by writing the desired base address selection into I/O port 0F8Dh bit 4 to bit 0, [b4..b0]. The port address can be read as `111b4, b3..b0, 1110' for the address port and `111b4, b3..b0, 1111' for the data port. Therefore, the possible address and data access ports can be any one from 0E0Eh-0FFEh (address port) and 0E0Fh-0FFFh (data port).
380-383/388-38B 388-38F
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(3) To access MCIR1-23, write the corresponding register index into the address access port and read (or write) the data from (or to) the data access port. This read or write is only possible if the correct password (E4h) has been written into Port 0F8Dh, or is disabled (0F8Dh[7] = 1). Tables 5-3 through 5-5 illustrate the necessary steps to access MCIR1-23. Table 5-6 gives the bit formats for the MCIR1-23.
Table 5-3
7 Port 0F8Dh Pass word protection for access to address or data port: 0 = Enable 1 = Disable
MCBase, Direct MC Register
6 5 4 3 2 1 0
MCBase Register (WO) Reserved These bits specify the address for MCIdx[8:4] and MCData[8:4]: (Refer to Table 5-4.) Address range = 00000 through 11111
Table 5-4
15 14
McBase, Index (MCIndx) and Data (MCData) Ports Address Range
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Index Port Address [15:0] 0 0 0 0 1 1 1 Specified by MCBase[4:0] (Refer to Table 5-3) Data Port Address [15:0] 0 0 0 0 1 1 1 Specified by MCBase[4:0] (Refer to Table 5-3) 1 1 1 1 1 1 1 0
Table 5-5
7
MCIdx and MCData Registers
6 5 4 MCIdx 3 2 1 0
0
0
0
Specifies which MCIR register is to be accessed. 00000 = Disable 00001 = MCIR1:Base/Type Configuration 00010 = MCIR2: Reserved 00011 = MCIR3: SB/WSS Configuration 00100 = MCIR4: User Programmable GP 00101 = MCIR5: Option 00110 = MCIR6: MIDI Interface 00111 = MCIR7: Semaphore Software 01000 = MCIR8: Reserved 01001 = MCIR9: Test Control 01010 = MCIR10: Test Control 01011 = MCIR11: Status 01100 = MCIR12: Test MCData (refer to Table 5-6) 01101 = MCIR13: PNP Status 01110 = MCIR14: PNP CSN 01111 = MCIR15: PNP READ_DATA 10000 = MCIR16: Volume Control 10001 = MCIR17: Serial EEPROM 10010 = MCIR18: CONFIG Status 10011 = MCIR19: FM Control 10100 = MCIR20: GPIO Control 10101 = MCIR21: Serial Audio Control 10110 = MCIR22: Serial Audio Control 10111 = MCIR23: Reserved Remaining combinations = Reserved
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Table 5-6
7 MCIR1 Sound Blaster I/O base address (SBBase): 0 = 220 1 = 240 MCIR2 Reserved Set to 0. BAUD 96 register BAUD96: This bit could be used by PDA devices to communicate with other devices 0 = Disabled, normal MIDI UART in RXD pin. 1 = Enabled, 9600 baud rate UART in RXD pin MCIR3 Reserved: Must be set to 0. Reserved: Must be set to 0 for normal operation in WSS. 000 = Disable 001 = IRQ7 010 = IRQ9 011 = IRQ10 Sound Blaster/Windows Sound System Configuration Register DAP IRQ select: 100 = IRQ11 101 = IRQ5 110 = Reserved 111 = Reserved DAP DMA select: 000 = Disabled 001 = DRQ0 010 = DRQ1 011 = DRQ3 100 = Disable 101 = DRQ0 110 = DRQ1 111 = DRQ3 DRQ1(1) DRQ1(1) DRQ0(1) DRQ0(1) Default = 00h Reserved Set to 0. Reserved
MC Indirect Registers
6 5 4 3 2 1 0 Default = 06h Game port: 0 = Disable 1 = Enable
Base/Type Configuration Register Windows Sound System I/O base address (WSBase): 00 = 530 01 = E80 10 = F40 11 = 640 CD-ROM interface: The sense of these bits is reversed during writes. To disable CD, write b'011'. 000 = Disabled 100 = Secondary IDE All others = Reserved
Default = 00h
(1) If CIR9[2] = 0 (Codec Indirect Register 9, bit 2), then DAP DMA[4:7] can be selected MCIR4 Playback FIFO flow control: 00 = Empty 01 = Full-2 10 = Full-4 11 = Not full User Programmable General Purpose Register OPL select: 00 = OPL2 01 = OPL3 10 = OPL4 11 = OPL5 Digital-Analog controller zero: 0 = Hold 1 = Clear Audio:(1) 0 = Disable 1 = Enable Default = 10h Sound Blaster version: 00 = 2.1 01 = 1.5 10 = 3.2 11 = 4.4
(1) Bit 2 can also accessed through the MC register or through PNP logic. MCIR5 Reserved Codec Expanded Mode:(1) 0 = Disable 1 = Enable Option Register Sound Blaster ADPCM: 0 = Disable 1 = Enable Command FIFO in Sound Blaster mode: 0 = Disable 1 = Enable Volume effect for Sound Blaster Pro mixer voice volume emulation: 0 = Disable 1 = Enable DMA watch dog timer: 0 = Disable 1 = Enable When enabled, the 82C931 will generate internal DACK after the DRQ pending time-up. Default = 00h Reserved
(1) Bit 5 must be set in order to access the CIR16-31, the Expanded Mode of the Codec Indirect Registers. Refer to Table 5-9 and Table 5-11.
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Table 5-6
7 MCIR6 MPU-401: 0 = Disable 1 = Enable MPU-401 base address select: 00 = 330 01 = 320 10 = 310 11 = 300
MC Indirect Registers (cont.)
6 5 4 3 2 1 0 Default = 00h Reserved Windows sound system mode: 0 = Disable 1 = Enable Sound Blaster mode: 0 = Disable 1 = Enable
MIDI Interface Register (WO) MPU-401 interrupt select: 00 = IRQ9 01 = IRQ10 10 = IRQ5 11 = IRQ7
MCIR7 D7 MCIR8 MCIR9 Digital power-down: 0 = Normal 1 = Powerdown MCIR10 Playback reset: 0 = Normal Capture reset: 0 = Normal Analog power-down: 0 = Normal 1 = Powerdown D6
Semaphore Software Register (Software use only) D5 D4 D3 D2 D1
Default = 00h D0 Default = 00h Default = 00h Software reset: 0 = Disable 1 = Enable
Reserved Register Test Control Register Reserved
Test Control Register PNP test mode: 0 = Normal Test (PNP logic is set to Sleep mode) Status Register (RO) Capture DMA pending? 0 = No 1 = Yes MPU interrupt pending? 0 = No 1 = Yes CD interrupt pending? 0 = No 1 = Yes Capture interrupt pending? 0 = No 1 = Yes Playback interrupt pending? 0 = No 1 = Yes Playback FIFO empty? 0 = No 1 = Yes Reserved
Default = 00h
1 = Reset (play- 1 = Reset (cap- 1 = back data ture data path clear, path clear, active high) active high) MCIR11 Playback DMA pending? 0 = No 1 = Yes MCIR12 Reserved
Default = 00h Capture FIFO empty? 0 = No 1 = Yes Default = 00h Digital test mode output select (WO)
Test Register Digital test mode output high/low byte select (WO) PNP Status Register (RO) Modem interface logical device: 0 = Disable 1 = Enable IDE logic device: 0 = Disable 1 = Enable MC logical device: 0 = Disable 1 = Enable CONFIG mode: 1 = 82C931's PNP logic is in the CONFIG mode ISOLATE mode: 1 = 82C931's PNP logic is in the ISOLATE mode SLEEP mode: 1 = 82C931's PNP logic is in the SLEEP mode
MCIR13 CSN not zero active high: 1 = PNP configuration manager assigned a CSN to 82C931.(1)
Default = 01h WAIT4KEY mode: 1 = 82C931's PNP logic is in the WAIT4KEY mode
(1) When a CSN is assigned to the 82C931, it switches to the PNP mode and the resource configuration is controlled through the PNP registers.
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Table 5-6
7 MCIR14
MC Indirect Registers (cont.)
6 5 4 3 2 1 0 Default = 00h
PNP CSN Register (RO)
PNP card select number: This registers shows the CSN assigned to the 82C931 by the PNP configuration manager. MCIR15 PNP Read Port Address Register (RO) Default = 00h
PNP READ_DATA port: This registers shows the READ_DATA port assigned by the PNP configuration manager. MCIR16 Reserved Push-bottom volume control interrupt enable UP bottom is pushed? 0 = No 1 = Yes This bit is cleared after a read. MCIR17 Write to external serial EEPROM: 0 = Disable 1 = Enable External serial EEPROM chip select: 0 = Disable 1 = Enable External serial EEPROM clock: 0 = Disable 1 = Enable Volume Control Register DOWN bottom is pushed? 0 = No 1 = Yes This bit is cleared after a read. Serial EEPROM Control Register External serial EEPROM data out: 0 = Disable 1 = Enable Connected to DIN of external EEPROM External serial EEPROM data out: 0 = Disable 1 = Enable Connected to DIN of external EEPROM External serial PNP setting EEPROM (R/W): capability (R/W) Read: When read for 0 = enabled status: 1 = disabled 0 = Disable Write: 1 = Enable 0 = disabled When write to 1 = enabled change: Note:the polar0 = Enable ity of the read 1 = Disable is the opposite Note: read of the write. polarity is the opposite of write's. Master volume mute control (active high) Push-bottom volume control interrupt status (RO) This bit is cleared after a read. Default = 00h Volume control interrupt select: 00 = Disable 01 = IRQ5 10 = IRQ10 11 = IRQ11
Default = 00h Reserved
MCIR18 Modem interface capability (R/W): When read for status: 0 = Disable 1 = Enable When write to change: 0 = Enable 1 = Disable Note: read polarity is the opposite of write's ASIO function: 0 = Disable 1 = Enable Reserved 0 = Default
CONFIG Status Register Mode 0 status (RO): reflects 931 pin#11 setting. 0 = 931-AD for adapter 1 = 931-MD for motherboard Chip Revision ID (RO) Silicon rev. 0.1 = 0x8 Silicon rev. 1.1 = 0x9
Default = xxh
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Table 5-6
7 MCIR19 IDE IRQ input routed to IRQ output: 0 = Disable 1 = Enable SDHOE function on pin 43 when configured for MB Mode: 0 = Disable 1 = Enable MCIR20 GPIO3 mapping: 0 = Pin 42 931-AD 1 = Pin 36 931-MB Note: GPIO3 pin type: 0 = Input 1 = Output GPIO2 mapping: 0 = Pin 41 931-AD 1 = Pin 35 931-MB GPIO Control Register 0 GPIO2 pin type: 0 = Input 1 = Output GPIO1 mapping: Pin 11 for 931-AD and 931-MB GPIO1 pin type: 0 = Input 1 = Output GPIO0 mapping: Pin 43 for 931-AD and 931-MB Default = 00h GPIO0 pin type: 0 = Input 1 = Output IRQ3, IRQ4: 0 = Disable 1 = Enable
MC Indirect Registers (cont.)
6 5 4 3 2 1 0 Default = xxh MEGA bass: 0 = Disable 1 = Enable OPTi mode for enhanced FM features: 0 = Disable 1 = Enable External FM select: 0 = Disable 1 = Enable
FM Control Register Reserved
GPIO function is available only when the specified pin is not being used for another function. Serial Audio Control Register 0 CTL_SEL[1:0] P2S_SEL[1:0] SAO data source selection 00/11 = From DMA Playback 01 = From FM 10 = From ADC, captured from analog section SPCDSEL Enables dual playback 0 = 2nd DMA channel is used for DMA capture 1 = 2nd DMA is used with 1st DMA channel for DMA playback ADCSEL Selects DMA data capture source 0 = ADC data (from analog section) 1 = SAI data FDACSEL Selects FDAC data source 0 = FDAC takes FM data 1 = FDAC takes SADI (if SPCDSEL=0), 2nd DMA playback data (if SPCDSEL=1) Default = 00h DACSEL Selects DAC data souce 0 = DMA playback 1 = SAI
MCIR21
ASIO shift clock selection 00/11 = Use the shift clock from internal FS 01 = Use FM timing 10 = Use external SCLK
MCIR22 Reset ASIO: 0 = Normal 1 = Reset ASIO test mode: 0 = Normal 1 = Test F16 Specify ASIO sample period data location: 0 = Last 16 bits of the L/R half sample period 1 = First 16/17 bits of L/R half sample period
Serial Audio Control Register 1 CLK32 Number of SLCKs in a sample period (delay-mode or pulse-mode ASIO only) 0 = 32 1 = >32 SCLK polarity: FSYNC polarity: PULSE Pulse mode type of serial data (AT&T7525 comp or CS8412 DSP) 0 = Not activated 1 = Activated
Default = 00h
0 = Reverse 0 = Reverse 1 = No changed 1 = No changed
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Table 5-6
7 MCIR23 ASDOOE ADO direction control 0 = Input 1 = Output SCLKOE SCLK direction control 0 = Input 1 = Output
MC Indirect Registers (cont.)
6 5 4 3 2 1 0 Default = 00h CLKSEL[1:0] Selects shift clock for serial audio data output (sclk_out) 00 = mclk/8 01 = mclk/4 10 = mclk/2 11 = mclk/1
Serial Audio Clock/Output Control Register FSYNCOE FSYNC direction control 0 = Input 1 = Output MCLKEN External MCLK enable (fed through ASDO) 0 = Disabled 1 = Enabled MCLKSEL[1:0] Master clock divider selection 00 = asdo_clk/8 01 = asdo_clk/4 10 = asdo_clk/2 11 = asdo_clk/1
MCIR24 JRDY/Game Port IRQ Readback of '1' indicates the game port counters are stopped and the interrups is generated. The IRQ is cleared by writing a '1' to this location. MCIR25 SOUNDIRQ Shows the status of the audio IRQ, a '1' indicates there is a soundIRQ
Game Port Counter Setup and Status Register GPIRQEN IRQ generation when the game port counter is finish counting 0 = Disabled 1 = Enabled GPWPEN Auto game port trigger (20x write) 0 = Disabled 1 = Enabled ACTBY By axis counter enable 0 = Disabled 1 = Enabled ACTBX Bx axis counter enable 0 = Disabled 1 = Enabled ACTAY Ay axis counter enable 0 = Disabled 1 = Enabled
Default = 00h ACTAX Ax axis counter enable 0 = Disabled 1 = Enabled
Game Port Counter Values Register GPCOUNT[7:0] Hardware counter values in H-byte L-byte fashion (16-bit). The sequence will be: Joystick A-X axis Joystick A-Y axis Joystick B-X axis Joystick B-Y axix
Default = xxh
The count value will be changed automatically upon each read of this register. If that particular joystick axis is maksed (disabled), the count will skip accordingly. MCIR26 JPTSTEN Game port counter test mode, counter toggled by 14.318MHz (default=1MHz) 0 = Disabled 1 = Enabled Reserved VCPIN FDAC Data Control Register ASWTST FDACMUL Multiply FDAC data by 2 0 = Disabled 1 = Enabled FMMUL Multiply FM data by 2 0 = Disabled 1 = Enabled FMDIV Divide FM data by 2 0 = Disabled 1 = Enabled Special volume FDAC data control pins auto-switching move the pins timer test mode, to TxD timer togup/down=GD5/ gled by 4 (normal: 14.318MHz up/down = (default = GD7/6 31KHz) 0 = Disabled 1 = Enabled 0 = Disabled 1 = Enabled Default = 00h AUTOSW Auto-detect of TxD activity to switch the FDAC data between FM and serial audio (which comes from TxD 0 = Disabled 1 = Enabled
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5.3 SBBase Register
ters (CPU Direct I/O R/W). Note that in Table 5-7, which gives the SBBase register bit formats, some registers may also be accessed through ALBase. However, use only one Base register for accessing. SBBase is mainly used to access the Digital Audio Processor (DAP) registers, however, as shown in Table 5-7 other types of registers are also accessible through SBBase. The indexing scheme is the same as when accessing MCBase regis-
Table 5-7
7
SBBase Registers for FM and DAP Applications
6 5 4 3 2 1 0
SBBase+00h (or ALBase+00h) SBBase+00h (or ALBase+00h) SBBase+01h (or ALBase+01h) SBBase+02h (or ALBase+02h) SBBase+03h (or ALBase+03h) SBBase+04h SBBase+05h SBBase+06h
Left FM Status Register (RO) Left FM Address Port Register (WO) Left FM Data Port Register (WO) Right FM Address Port Register (WO) Right FM Data Port Register (WO) Mixer Address Port Register (WO) Mixer Data Port Register (WO) DAP Reset Register Don't care DAP software reset at end of the I/O write command: 0 = Disable 1 = Enable(1)
(1) When bit 0 is enabled, it sets a software reset flag. This software reset is terminated by performing another write at this location with bit 0 = 0. A system reset will reset the software reset flag, thus terminating the software reset SBBase+08h SBBase+08h SBBase+09h SBBase+0Ah SBBase+0Ch SBBase+0Ch DAP Input buffer full:(1) 0 = Empty 1 = Full (1) This flag is set when the host CPU writes data in the input data bus buffer and cleared when the data is read by the internal DAP. FM Status Port Register (RO) FM Address Port Register (WO) FM Data Port Register (WO) DAP Read Data Register (RO) DAP Data/Command Register (WO) DAP Write Buffer Status Register (RO) SBBase+A[6:0]
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Table 5-7
7 SBBase+0Eh DAP output buffer is full:(1) 0 = Empty 1 = Full (1) This flag is set in the DAP when data is written in the output data bus buffer and cleared when the host CPU or the DMA controller reads the data in the output data bus buffer. Note: Reading this register will also clear the Digital Audio Processor interrupt request.
SBBase Registers for FM and DAP Applications (cont.)
6 5 4 3 2 1 0
DAP Output Buffer Status Register (RO Output Buffer
5.4
WSBase Register
Direct I/O R/W). The bit formats for WSS-related registers are given in Table 5-8 and Table 5-9 shows the Codec-related registers.
Two types of registers can be accessed through WSBase: * Windows Sound System (WSS) and Codec registers These registers are accessed through the WSBase register and use the same type of indexing scheme as MCBase (CPU
Table 5-8
7
WSBase Registers for Windows Sound System Applications
6 5 4 3 2 1 0 Default = 00h WSS DRQ select: 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = Playback Disable DRQ0 DRQ1 DRQ3 Disabled DRQ0 DRQ1 DRQ3 Capture Disable Disable Disable Disable DRQ1 DRQ1 DRQ0 DRQ0 Default = 00h
WSBase+00h-03h Reserved IRQ sense source: 0 = Normal 1 = auto-interrupt selection
WSS Configuration Register (W0) WSS IRQ select: 000 = Disable 001 = IRQ7 010 = IRQ9 011 = IRQ10 100 = IRQ11 101 = IRQ5 110 = Reserved 111 = Reserved
WSBase+00h-03h Channel available: 0 = DRQ0/1/3 and IRQ7/9/10/ 11 available 1 = DRQ1/3 and IRQ7/9 available IRQ sense: 0 = No interrupt 1 = WSS interrupt active
WSS Version Register (R0) Version: 04h
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Note that at the Codec Index Address Register (WSBase+04h), bits 4 through 0 are used as the index address for accessing the Codec Indirect Registers (CIR). A write to or a read from the Codec Indexed Data Register (WSBase+05h) will access the Indirect Register which is indexed by the value most recently written to the Codec Index Address Register. There are 31 Codec Indirect Registers, CIR0-CIR15 are accessed normally. To access CIR16 through CIR31, Expanded Mode registers, MCIR12[5] = 1 (MCBase Indirect Register, bit 5). Table 5-10 gives the bit formats for CIR0CIR15 and Table 5-11 shows CIR16-CIR31.
Table 5-9
7 WSBase+04h Initialization: This bit is set when the codec is in a state which cannot respond to parallel bus cycles.(1)
WSBase Register for Codec/Mixer Applications
6 5 4 3 2 1 0 Default = 00h
Codec Index Address Register (R/W, exists in Codec and shadowed in 82C931) Mode change: 0 = Disable 1 = Enable Transfer request:(2) Index address:
These bits specify which Codec Indirect Register (CIR) is to be accessed. Note CIR16 through CIR31 are Expanded Modes and require that MCIR12[5] = 1. 0 = Transfers (Refer to Table 5-10 and Table 5-11 for these registers bit formats.) enabled during interrupt Expanded Mode Registers 1 = Transfers 00000 = CIR0: MIXOUTL Output Cntrl 10000 = CIR16: AUXL Input Cntrl disabled by 00001 = CIR1: MIXOUTR Output Cntrl 10001 = CIR17: AUXR Input Cntrl interrupt 00010 = CIR2: CDL Input Cntrl 10010 = CIR18: LINEL Input Cntrl 00011 = CIR3: CDR Input Cntrl 10011 = CIR19: LINER Input Cntrl 00100 = CIR4: FML Input Cntrl 10100 = CIR20: MICL Input Cntrl 00101 = CIR5: FMR Input Cntrl 10101 = CIR21: MICR Input Cntrl 00110 = CIR6: DACL Input Cntrl 10110 = CIR22: OUTL Gain Cntrl 00111 = CIR7: DACR Input Cntrl 10111 = CIR23: OUTR Gain Cntrl 01000 = CIR8: Fs & Playback Data Format 11000 = CIR24: Reserved 01001 = CIR9: Interface Configuration 11001 = CIR25: Reserved 01010 = CIR10: Pin Cntrl 11010 = CIR26: Reserved 01011 = CIR11: Error Status & Initialization 11011 = CIR27: Reserved 01100 = CIR12: Mode and ID (Mode 2 Bit) 11100 = CIR28: Capture Data Format 01101 = CIR13: Reserved 11101 = CIR29: Reserved 01110 = CIR14: Playback Upper Base 11110 = CIR30: Capture Upper Base 01111 = CIR15: Playback Lower Base 11111 = CIR31: Capture Lower Base
(1) Immediately after reset and once the codec has left the initialization state, the initial value of this register will be "0100 0000" (40h). During codec initialization, the Codec Index Register cannot be written and is always read 1000 0000 (80h). (2) When bit 5 is set, DMA transfers cease when bit 0 of the Codec Status Register (WSBase+06h) = 1. WSBase+05h Codec Indexed Data Register (R/W, exists in Codec only) Contains the contents of the Codec register referenced by the Index Data Register. During codec initialization, this register cannot be written and is always read as "1000 0000" (80h). Default = 00h
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Table 5-9
7 WSBase+06h PIO capture data is ready for upper or lower byte (RO): 0 = Lower 1 = Upper (or any 8-bit mode) PIO capture data is waiting for right or left channel ADC (RO): 0 = Right 1 = Left (or mono)
WSBase Register for Codec/Mixer Applications (cont.)
6 5 4 3 2 1 0 Default = 44h PIO Playback Data Register ready for more data (RO):(1) 0 = Valid DAC data (do not overwrite) 1 = Stale DAC data (ready for next host data write value) Interrupt: 0 = Disable 1 = Enable
Codec Status Register (R/W, exists in Codec only) PIO Capture Data Register contains data ready for reading by host (RO):(1) Sample over/underrun (RO): PIO playback data is needed for upper or lower byte (RO): PIO playback data is needed for right or left channel DAC (RO): 0 = Right 1 = Left (or mono)
Indicates that the most recent sample was not 0 = Lower 1 = Upper (or 0 = Stale ADC serviced in time; data (do not re- therefore either any 8-bit mode) an overrun for read) ADC capture or 1 = Fresh ADC underrun for data (ready for DAC playback next host data has occurred.(2) read)
(1) These bits (5 and 1) should only be programmed when direct programmed I/O data transfers are desired. (2) If both capture and playback are enabled, the source which set bit 4 ca be determined by reading COR and PUR. Bit 4 changes on a sample-by-sample basis. Note: Bits 5, 1, and 0 can change asynchronously to host accesses. The host may access this register while the bits are transitioning. The host read may return a zero value just as these bits are changing (e.g., a value of 1 would not be read until the next host access). This register's initial state after reset is "1100 1100". Codec Direct Data Register - Capture Mode (RO, exists in Codec only) Default = 00h
WSBase+07h
The Codec Direct Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0). During initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read "1000 0000" (80h). PIO Capture Data Register: This is the control register where capture data is read during programmed I/O data transfers. The reading of this register will increment the state machine so that the following read will be from the next appropriate byte in the sample. The exact byte which is next to be read can be determined by reading the Status Register. Once all relevant bytes have been read, the state machine will stay pointed to the last byte of the sample until a new sample is received from the ADCs. Once this has occurred, the state machine and status register will point to the first byte of the sample. Until a new sample is received, reads from this register will return the most significant byte of the sample. WSBase+07h Codec Direct Data Register - Playback Mode (WO, exists in Codec only) Default = 00h
The Codec Direct Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0). During initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read "1000 0000" (80h). PIO Playback Data Register: This is the control register where playback data is written during programmed I/O data transfers. Writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this port are ignored. The state machine is reset when the current sample is sent to the DACs.
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Table 5-10
D7 CIR0 Source select: 00 = LINE 01 = CD 10 = MIC 11 = MIXER MIC +20dB Gain: 0 = Disable 1 = Enable
Codec Indirect Registers
D6 D5 D4 D3 D2 D1 D0 Default = 00h Gain select for MIXOUTL (dB): 0000 = 0 0001 = +1.5 0010 = +3.0 0011 = +4.5 0100 = +6.0 0101 = +7.5 MIXOUTR Output Control Register 0110 = +9.0 0111 = +10.5 1000 = +12.0 1001 = +13.5 1010 = +15.0 1011 = +16.5 1100 = +18.0 1101 = +19.5 1110 = +21.0 1111 = +22.5
MIXOUTL Output Control Register Reserved
CIR1 Source select: 00 = LINE 01 = CD 10 = MIC 11 = MIXER MIC +20dB Gain: 0 = Disable 1 = Enable
Default = 00h Gain select for MIXOUTR (dB): Refer to CIR0[3:0] for decode.
Reserved
CIR2 Mute: 0 = Disable 1 = Enable Reserved
CDL Input Control Register Gain select for CDL (dB): 0000 = +12 0001 = +9 0010 = +6 0011 = +3 0100 = 0 0101 = -3 Note: 0110 = -6 0111 = -9 1000 = -12 1001 = -15 1010 = -18 1011 = -21 1100 = -24 1101 = -27 1110 = -30 1111 = -33
Default = 88h Reserved
This decode is also applicable for the MIC, LINE, AUX, and FM inputs. Default = 88h Reserved
CIR3 Mute: 0 = Disable 1 = Enable CIR4 Mute: 0 = Disable 1 = Enable CIR5 Mute: 0 = Disable 1 = Enable Reserved Reserved Reserved
CDR Input Control Register Gain select CDR (dB): Refer to CIR2[4:1] for decode.
FML Input Control Register Gain select FML (dB): Refer to CIR2[4:1] for decode.
Default = 88h Reserved
FMR Input Control Register Gain select FMR (dB): Refer to CIR2[4:1] for decode.
Default = 88h Reserved
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Table 5-10
D7 CIR6 Mute: 0 = Disable 1 = Enable Reserved *00000 = 0 00001 = -1.5 00010 = -3.0 00011 = -4.5 00100 = -6.0 00101 = -7.5 00110 = -9.0 00111 = -10.5
Codec Indirect Registers (cont.)
D6 D5 D4 D3 D2 D1 D0 Default = 80h
DACL Input Control Register Gain select for DAC inputs (dB): 01000 = -12.0 01001 = -13.5 01010 = -15.0 01011 = -16.5 01100 = -18.0 01101 = -19.5 01110 = -21.0 01111 = -22.5 10000 = -24.0 10001 = -25.5 10010 = -27.0 10011 = -28.5 10100 = -30.0 10101 = -31.5 10110 = -33.0 10111 = -34.5
11000 = -36.0 11001 = -37.5 11010 = -39.0 11011 = -40.5 11100 = -42.0 11101 = -43.5 11110 = -45.0 11111 = -46.5 Default = 80h
CIR7 Mute: 0 = Disable 1 = Enable CIR8 Audio data format - linear PCM or companded for all input and output data (used in conjunction with bit 5):(1) 000 = Linear, 8-bit unsigned 001 = -law, 8-bit companded 010 = Linear, 16-bit two's complement, Little Endian 011 = A-Law, 8-bit companded 100 = Reserved 101 = ADPCM, 4-bit, IMA compatible 110 = Linear, 16-bit two's complement, Big Endian 111 = Reserved Note: Bit 7 is not available in Mode 1 (forced to 0). Reserved
DACR Input Control Register Gain select for DAC inputs (dB): Refer to CIR6[4:0] for decode.
Fs and Playback Data Format Register Stereo/mono:(2) 0 = Mono 1 = Stereo Clock frequency divide / audio sample rate frequency: 0000 = 8.0kHz 0010 = 16.0kHz 0100 = 27.42857kHz 0110 = 32.0kHz 1000 = Reserved 1010 = Reserved 1100 = 48.0kHz 1110 = 9.6kHz
Default = 00h
0001 = 5.5125kHz 0011 = 11.025kHz 0101 = 18.9kHz 0111 = 22.05kHz 1001 = 37.8kHz 1011 = 44.1kHz 1101 = 33.075kHz 1111 = 6.615kHz
(1) SB/WSS mode switch: In Sound Blaster mode, the software driver should set CDF to 8 bit PCM mode (R8: FM1,FM-,C_L). (2) Selecting stereo results with alternating samples representing left and right audio channels. Mono playback plays the same audio sample on both channels. Mono capture only captures data from the left audio channel. Note: The contents of this register can only be changed if the mode change bit (WSBase+04h[6]) is enabled (set to 1). Writes to this register without the mode change bit enabled will have no affect. Interface Configuration Register Transfer playback data via DMA or PIO: 0 = DMA 1 = PIO Reserved Autocalibrate: 0 = Disable 1 = Enable (autocalibration after power down/reset or mode change DMA channel mode:(1) 0 = Dual 1 = Single Capture data in format selected:(2) 0 = Disable 1 = Enable Default = 00h Playback data in format selected:(3) 0 = Disable 1 = Enable
CIR9 Transfer capture data via DMA or PIO: 0 = DMA 1 = PIO
(1) In Sound Blaster mode, bit 2 is set when playback or capture DMA starts and is reset when DMA ends. (2) The codec generates CDRQ and responds to CDAK# when bit 1 = 1 and bit 7 = 0. If bit 7 = 1, bit 1 enables PIO capture mode. (3) The codec generates PDRQ and repents to PDAK# when bit 0 = 1 and bit 6 = 0. If bit 6 = 1, bit 1 enables PIO playback mode
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Table 5-10
D7 CIR10 Reserved
Codec Indirect Registers (cont.)
D6 D5 D4 D3 D2 D1 D0 Default = 00h Interrupt pin:(1) Reserved
Pin Control Register
0 = Disable 1 = Enable (Interrupt pin goes active high when the number of samples programmed in the Base Count Register is reached.) 2. In Sound Blaster mode, the software driver should set bit 1 = 1. CIR11 Capture overrun:(1) This bit is set when capture data has not been read by the host before the next sample arrives. The sample being read will not be overwritten by the new sample. The new sample is ignored. Playback underrun:(1) This bit is set when playback data has not arrived from the host in time to be played. This results in a midscale value sent to the DACs. Error Status and Initialization Register (RO) Autocalibration state: 0 = In progress 1 = Not in progress Current status of PDRQ and CDRQ: 0 = Inactive (low) Indicates under/over range on right input channel:(1) 0 = Less than -1dB under range Default = 00h Indicates under/over range on left input channel:(1) 0 = Less than -1dB under range
1 = Between -1dB and 0dB under 1 = Between -1dB and 0dB under range range 2 = Between 0dB and +1dB over range
1 = Active (high) 2 = Between 0dB and +1dB over range
3 = Greater than +1dB over range 3 = Greater than +1dB over range
(1) Bit changes on a sample-by-sample basis. (2) The occurrence of a capture overrun and/or playback underrun is designated in the Status Register's sample overrun/underrun bit (WSBase+06h[4]). The sample overrun/underrun bit is the logical OR of bits 7 and 6. This enables a polling host CPU to detect an overrun/underrun condition while checking other status bits. CIR12 Reserved ID Register Revision ID (RO): These bits define the revision level of the codec. CIR13 CIR14 Reserved Playback Upper Base Count Register Upper Base Count: This byte is the upper byte of the base count register containing the eight most significant bits of the 16-bit base register. Reads from this register return the same value which was written The current count contained in the counters can not be read. When enabled for SB Mode, this register is used for both the Playback and Capture Base Registers. Default = 00h Default = 00h Default = 0Ah
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Table 5-10
D7 CIR15
Codec Indirect Registers (cont.)
D6 D5 D4 D3 D2 D1 D0 Default = 00h
Playback Lower Base Count Register Lower Base Count:
This byte is the lower byte of the base count register containing the eight least significant bits of the 16-bit base register. Reads from this register return the same value which was written The current count contained in the counters can not be read. When enabled for SD Mode, this register is used for both the Playback and Capture Base Registers.
Table 5-11
7 CIR16 Mute: 0 = Disable 1 = Enable CIR17 Mute: 0 = Disable 1 = Enable CIR18 Mute: 0 = Disable 1 = Enable CIR19 Mute: 0 = Disable 1 = Enable CIR20 Mute: 0 = Disable 1 = Enable
Expanded Mode CIR
6 5 4 3 2 1 0 Default = 88h Reserved
AUXL Input Control Register Reserved Gain select for AUXL (dB): Refer to CIR2[4:1] for decode.
AUXR Input Control Register Reserved Gain select for AUXR (dB): Refer to CIR2[4:1] for decode.
Default = 88h Reserved
LINEL Input Control Register Reserved Gain select for LINEL (dB): Refer to CIR2[4:1] for decode.
Default = 88h Reserved
LINER Input Control Register Reserved Gain select for LINER inputs (dB): Refer to CIR2[4:1] for decode.
Default = 88h Reserved
MICL Input Control Register MICR mixed into OUTL: 0 = Disable 1 = Enable MICR Input Control Register MICL mixed into OUTR: 0 = Disable 1 = Enable Reserved Gain select for MICR (dB): Refer to CIR2[4:1] for decode. Reserved Gain select for MICL (dB): Refer to CIR2[4:1] for decode.
Default = 88h Reserved
CIR21 Mute: 0 = Disable 1 = Enable
Default = 88h Reserved
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Table 5-11
7 CIR22 Mute: 0 = Disable 1 = Enable Reserved 00000 = 0 00001 = -3 00010 = -6 00011 = -9 00100 = -12 00101 = -15 00110 = -18 00111 = -21
Expanded Mode CIR (cont.)
6 5 4 3 2 1 0 Default = 80h Reserved 11000 = -72 11001 = -75 11010 = -78 11011 = -81 11100 = -84 11101 = -87 11110 = -90 11111 = -93 Default = 80h Reserved
OUTL Output Control Register Gain select for OUTL (dB): 01000 = -24 01001 = -27 01010 = -30 01011 = -33 01100 = -36 01101 = -39 01110 = -42 01111 = -45 10000 = -48 10001 = -51 10010 = -54 10011 = -57 10100 = -60 10101 = -63 10110 = -66 10111 = -69
CIR23 Mute: 0 = Disable 1 = Enable CIR24-CIR27 CIR28 Audio data format - linear PCM or companded for all input and output data (used in conjunction with bit 5):(1) 000 = Linear, 8-bit unsigned 001 = -law, 8-bit companded 010 = Linear, 16-bit two's complement, Little Endian 011 = A-Law, 8-bit companded 100 = Reserved 101 = ADPCM, 4-bit, IMA compatible 110 = Linear, 16-bit two's complement, Big Endian 111 = Reserved Note: Bit 7 is not available in Mode 1 (forced to 0). Reserved
OUTR Output Control Register Gain select for OUTR (dB): Refer to CIR22[5:1] for decode.
Reserved Capture Data Format Stereo/mono:(2) 0 = Mono 1 = Stereo Reserved
Default = 00h Default = 00h
(1) SB/WSS mode switch: In Sound Blaster mode, the software driver should set CDF to 8 bit PCM mode (R8: FM1,FM-,C_L). (2) Selecting stereo results with alternating samples representing left and right audio channels. Mono playback plays the same audio sample on both channels. Mono capture only captures data from the left audio channel. Note: The contents of this register can only be changed if the mode change bit (WSBase+04h[6]) is enabled (set to 1). Writes to this register without the mode change bit enabled will have no affect. Reserved Capture Upper Base Count Upper Base Count: This byte is the upper byte of the base count register containing the eight most significant bits of the 16-bit base register. Reads from this register return the same value which was written. CIR31 Capture Lower Base Count Upper Base Count: This byte is the lower byte of the base count register containing the eight most significant bits of the 16-bit base register. Reads from this register return the same value which was written. Default = 00h Default = 00h Default = 00h
CIR29 CIR30
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6.0 Electrical Specifications
Stresses above those listed in the following tables may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied.
6.1
VCC AVCC VIN VOUT TOP TSTG ESD *
*
Absolute Maximum Ratings
Parameter Supply Voltage Analog Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature ESD Tolerance (Human Body Model MIL883C, 3015.7, Notice 8) Min 4.5 4.75 -0.5 -0.5 0 -40 Max 5.5 5.25 VCC + 0.5 VCC + 0.5 70 125 1000 Unit V V V V C C V
Symbol
ESD senstive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the 82C931 features ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
6.2
VIL VIH VIHa VOL VOH IIL IILa IILb IOL IPD
DC Characteristics: 5.0 Volt (VCC = 5.0V 5%, TA = 0C to +70C)
Parameter Low Level Input Voltage High Level Input Voltage High Level Input Voltage for RESET Low Level Output Voltage High Level Output Voltage Input Leakage Current Input Leakage Current with 5K ohm Pull-up Resistor Input Leakage Current with 50K ohm Pull-up Resistor Output Leakage Current Static or Power-down Mode Current -100 -10 VCC - 0.5 Min -0.3 2.4 3.5 Max 0.8 VCC + 0.3 VCC + 0.3 0.2 5.5 10 -500 -50 10 300 Unit V V V V V A A A A A Condition VCC = 5.5V VCC = 4.5V VCC = 4.5V IOL = 4mA, VCC = 4.5 IOH = -4mA VCC = 5.5V VCC = 5.5V VIN = 0V VIN = 0V VCC = 5.5V VCC = 5.5V
Symbol
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6.3
IIL IIH IOZ VV+ VH VIL VIH VOL VOH RPD RPU CIN COUT CIO IOS IKLU VESD
General Specifications: 5.0 Volt (VCC = 5.0V 5%, TA = 0C to +70C)
Parameter Low Level Input Current High Level Input Current Tristate Output Leakage Current Schmitt Negative Threshold Schmitt Positive Threshold Schmitt Hysteresis low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Pull-down Resistance Pull-up Resistance Input Capacitance Output Capacitance Bidirectional Capacitance Short Circuit Output Current I/O Latch-Up Current Electrostatic Protection 100 2000 2 2.4 50 50 200 200 5 5 5 25 2.0 0.4 Min -10 -10 -10 0.8 1.5 1.4 2.5 0.6 1.0 0.8 Typ Max 10 10 10 1.3 2.5 2.1 3.5 Unit A A A V V V V V V V K K pF pF pF mA mA V Condition VIN = GND VIN = VCC VOUT = 0/VCC TTL-STATIC CMOS-STATIC TTL-STATIC CMOS-STATIC TTL-STATIC CMOS-STATIC TTL-STATIC TTL-STATIC TTL-STATIC TTL-STATIC VIN = VCC VIN = VCC Frequency = 1MHZ @ 0V Frequency = 1MHZ @ 0V Frequency = 1MHZ @ 0V VOUT = 0V V < GND, V > VCC C = 100pF, R = 1.5K
Symbol
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6.4
Inputs MICR, MICL, LINER, LINEL, CDR, CDL, AUXR, AUXL, CINR, CINL Outputs OUTR, OUTL MIXOUTR, MIXOUTL VREF1 VREF2 Signal Bandwidth Output Range Signal Bandwidth Output Range 10 0.5 10 1.75 1.85 20K 3.0 20K Hz V Hz V Sine Wave Load = 10K, 25pF Sine Wave DC DC Signal Bandwidth Input Range 10 0.5 20K 3.0 Hz V Sine Wave
Pin Specifications - Analog (VCC = 5.0V, 25C)
Parameter Min Typ Max Unit Condition
Pin Name
6.5
Volume Setting
Min -33 0 -93 -46.5 2.6 1.3 2.6 2.0 1.3 3.0 1.5 3.0 3.0 1.5 -80 -80 0.04 80 60 -0.5 100 0.5 Typ Max 12 22.5 0 0 dB 3.4 1.7 3.4 4.0 1.7 dB dB % dB dB dB ppm/C Unit dB Test Conditions Input @ 1Hz, 2.5Vpp wrt ACOM
Parameter Input Gain/Atten. Range: 16 levels (MIC, LINE, CD, AUX) 16 levels (ADC) 32 levels (DAC) 32 levels (LOUT) Step Size: 16 levels (MIC, LINE, CD, AUX) 16 levels (ADC) 32 levels (DAC) 32 levels (LOUT) Mute Level Signal to Noise Ratio Total Harmonic Distortion Total Dynamic Range Interchannel Isolation Interchannel Gain Mismatch Gain Drift
90 to -81dB) (-84 to -93dB)
6.6
Analog Characteristics
Test conditions Temp=25 C, VDD, VCC=+5v, Input signal= 1kHz sine wave, Analog output passband: 20 Hz to 20kHz, Sample freq = 44.1 kHz
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DAC test conditions 16-bit linear mode, Full Scale input, 10 k output load, measured at Line Out. ADC test conditions 16-bit linear mode, 0 dB Gain, Line Input.
6.6.1
Analog Inputs
Min 2.6 Typ 2.8 Max 3.1 Units Vp-p
Parameters Input voltage LINE/CD/AUX/CIN MIC with 0dB gain MIC with 20dB gain Input impedance Input capacitance
2.6 0.26 10
2.8 0.28 20
3.1 0.31
Vp-p Vp-p k
15
pF
6.6.2
Analog Outputs (10k, 25pF)
Min 2.5 Typ 2.8 1.85 600 10 Max 3.1 Units Vp-p Volts W k
Parameters Full-scale output voltage (OUTR & OUTL) Vref Output impedance External load impedance
6.6.3
Volume Settings
Min 1.3 Typ 1.5 46.5 80 Max 1.7 Units dB dB dB
Parameter Master volume step size Master volume output atten range Mute level
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6.6.4 Analog-to-Digital Converters
Min Typ 16 75 85 .025 80 Max Units bits dB % dB
Parameters Resolution Total dynamic range THD Interchannel isolation: Line to Line/CD/Aux/Mic Interchannel gain mismatch Gain drift
-0.5 100
+0.5
dB ppm/C
6.6.5
Digital-to-Analog Converters
Min Typ 16 78 95 .022 80 Max Units bits dB % dB
Parameters Resolution Total dynamic range THD Interchannel isolation:
Interchannel gain mismatch Gain drift
-0.5 100
+0.5
dB ppm/C
6.7
AC Timings
Parameter Min Max Unit Condition
Symbol ISA Bus tOSCP tOSCH tOSCL tSCKP tSCKH tSCKL tRST tCMDW tWDSU tWDHD tRAC
OSC (14.318MHz) Frequency OSC High Width OSC Low Width SYSCLK Frequency SYSCLK High Width SYSCLK Low Width RESET to RESET# IOR#/IOW# Command Width Write Data Setup to IOW# Rising Write Data Hold from IOW# Rising Read Access Time
14.0 32 32 8 50 55 40 120 30 15 20
14.5 40 40 9 70 70 80
MHz ns ns MHz ns ns ns ns ns ns
50
ns
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Symbol tASU tAHD tDKSU tDKHD tDHR tDRHD CD-ROM tCA tXCS tCMDD SA to CA Delay SA to IDECS1#/3# IOR#/IOW# to XIOR#/XIOW# Delay 3 5 3 20 20 20 ns ns ns Parameter Address Setup to IOR#/IOW# Falling Address Hold from IOR#/IOW# Rising DACK# Setup to IOR#/IOW# Falling DACK# Hold from IOR#/IOW# Rising SD Hold from IOR# Rising DRQ Hold from IOR#/IOW# Falling Min 50 30 40 160 0 0 20 25 Max Unit ns ns ns ns ns ns Condition
Figure 6-1
RESET and CLK Timing Waveform
tOSCH tOSCL
OSC
RESET tRST RESET#
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Figure 6-2 CD-ROM I/O Read Cycle
SA[15:0] tAHD SD[7:0] tRDHD tCMDW IOR# tASU tCA CA[2:0] tXCS IDECSn# tCMDD XIOR#
Note: For the above timing, AEN = 0, DRQ = 0, and DACKn# = 1.
Figure 6-3
CD-ROM I/O Write Cycle
SA[15:0] tAHD SD[7:0] tWDSU tCMDW IOW# tASU tCA CA[2:0] tXCS IDECSn# tCMDD XIOW# tWDHD
Note: For the above timing, AEN = 0, DRQ = 0, and DACKn# = 1.
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Figure 6-4 DMA Write/Playback Cycle
DRQ DACKn# tDKHD SD[7:0] tDKSU tCMDW IOW# tCMDD XIOW# Note: For the above timing, AEN = 1. tWDHD
Figure 6-5
DMA Read/Capture Cycle
DRQ DACKn# tDKHD SD[7:0] tDKSU tCMDW IOR# tCMDD XIOR# Note: For the above timing, AEN = 1. tRDHD
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7.0 Mechanical Packages
100-pin PQFP, Plastic Quad Flat Pack
Figure 7-1
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Figure 7-2 100-pin TQFP, Thin Quad Flat Package
Note:
Pinout for TQFP package is identical to pinout of PQFP package.
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Sales Information
HEADQUARTERS:
OPTi Inc. 888 Tasman Drive Milpitas, CA 95035 tel: 408-486-8000 fax: 408-486-8011
Michigan
Jay Marketing 44752 Helm Street., Ste. A Plymouth, MI 48170 tel: 313-459-1200 fax: 313-459-1697
Wisconsin
Micro-Tex, Inc. 22660 Broadway, Ste. #4A Waukesha, WI 53186 tel: 414-542-5352 fax: 414-542-7934
Singapore
Instep Microsolutions Pte Ltd. 18, Tannery Lane, #05-02 Lian Tong Building Singapore 347780 tel: 65-741-7507 fax: 65-741-1478
New Jersey
SALES OFFICES:
Japan
OPTi Japan KK Murata Building 6F, 2-22-7 Ohhashi Meguro-ku Tokyo 153, Japan tel: 81-3-5454-0178 fax: 81-3-5454-0168
S-J Associates, Inc. 131-D Gaither Dr. Mt. Laurel, NJ 08054 tel: 609-866-1234 fax: 609-866-8627
International
Australia
Braemac Pty. Ltd. Unit 6, 111 Moore St., Leichhardt Sydney, 2040 Australia tel: 61-2-550-6600 fax: 61-2-550-6377
South America
Uniao Digital Rua Guido Caloi Bloco B, Piso 3 Sao Paulo-SP, CEP 05802-140 Brazil tel: 55-11-5514-3355 fax: 55-11-5514-1088
New York
S-J Associates, Inc. 265 Sunrise Highway Rockville Centre, NY 11570 tel: 516-536-4242 fax: 516-536-9638 S-J Associates, Inc. 735 Victor-Pittsford Victor, NY 14564 tel: 716-924-1720
China
Switzerland
Taiwan
OPTi Inc. 9F, No 303, Sec 4, Hsin Yih Road Taipei, Taiwan, ROC tel: 886-2-325-8520 fax: 886-2-325-6520
Legend Electronic Components. Ltd. Datacomp AG Silbernstrasse 10 Unit 413, Hong Kong Industrial 8953 Dietikon Technology Centre Switzerland 72 Tat Chee Avenue tel: 41-1-740-5140 Kowloon Tong, Hong Kong fax: 41-1-741-3423 tel: 852-2776-7708 fax: 852-2652-2301
United States
OPTi Inc. 20405 State Highway 249, Ste. #220 Houston, TX 77070 tel: 281-257-1856 fax: 281-257-1825
United Kingdom
North & South Carolina
Concord Component Reps 10608 Dunhill Terrace Raleigh, NC 27615 tel: 919-846-3441 fax: 919-846-3401
France
Tekelec Airtronic, France 5, Rue Carle Vernet 92315 Sevres Cedex France tel: 33-1-46-23-24-25 fax: 33-1-45-07-21-91
REPRESENTATIVES: United States
Alabama/Mississippi
Concord Component Reps 190 Line Quarry Rd., Ste. #102 Madison, AL 35758 tel: 205-772-8883 fax: 205-772-8262
Ohio/W. Pennsylvania
Lyons Corp. 4812 Fredrick Rd., Ste. #101 Dayton, OH 45414 tel: 513-278-0714 fax: 513-278-3609 Lyons Corp. 4615 W. Streetsboro Richfield, OH 44286 tel: 216-659-9224 fax: 216-659-9227 Lyons Corp. 248 N. State St. Westerville, OH 43081 tel: 614-895-1447 fax: Same
Spectrum 2 Grange Mews, Station Road Launton, Bicester Oxfordshire,OX6 0DX UK tel: 44-1869-325174 fax: 44-1869-325175 MMD 3 Bennet Court, Bennet Road Reading Berkshire, RG2 0QX UK tel: 44 1734 313232 fax: 44 1734 313255
Germany
Kamaka Rheinsrasse 22 76870 Kandel Germany tel: 49-7275-958211 fax: 49-7275-958220
India
Spectra Innovation Unit S-822 Manipal Centre 47 Dickenson Road Bangalore 560-042 Kamataka, India tel: 91-80-558-8323/3977 fax: 91-80-558-6872
Florida
Engineered Solutions Ind., Inc. 1000 E. Atlantic Blvd., Ste. #202 Pompano Beach, FL 33060 tel: 305-784-0078 fax: 305-781-7722
Georgia
Concord Component Reps 6825 Jimmy Carter Blvd., Ste. #1303 Norcross, GA 30071 tel: 770-416-9597 fax: 770-441-0790
Israel
Ralco Components (1994) Ltd. 11 Benyamini St. 67443 Tel Aviv Israel tel: 972-3-6954126 fax: 972-3-6951743
Texas
Axxis Technology Marketing, Inc. 701 Brazos, Suite 500 Austin, TX 78701 tel: 512-320-9130 fax: 512-320-5730 Axxis Technology Marketing, Inc. 6804 Ashmont Drive Plano, TX 75023 tel: 214-491-3577 fax: 214-491-2508
Illinois
Micro-Tex, Inc. 1870 North Roselle Rd., Ste. #107 Schaumburg, IL 60195-3100 tel: 708-885-8200 fax: 708-885-8210
Korea
Woo Young Tech Co., Ltd. 5th Floor Koami Bldg 13-31 Yoido-Dong Youngduengpo-Ku Seoul, Korea 150-010 tel: 02-369-7099 fax: 02-369-7091
Virginia
S-J Associates, Inc. 900 S. Washington St., Ste. #307 Falls Church, VA 22046 tel: 703-533-2233 fax: 703-533-2236
Massachusetts
S-J Associates, Inc. 267 Boston Road Corporate Place, Ste. #3 N. Billerica, MA 01862 tel: 508-670-8899 fax: 508-670-8711
The information contained within this document is subject to change without notice. OPTi Inc. reserves the right to make changes in this manual at any time as well as in the products it describes, at any time without notice or obligation. OPTi Inc. assumes no responsibility for any errors contained within. In no event will OPTi Inc. be liable for any damages, direct, indirect, incidental or consequential resulting from any error, defect, or omission in this specification. Copyright (c) 1997 by OPTi Inc. All rights reserved. OPTi is a trademark of OPTi Incorporated. All other brand and product names are trademarks or copyrights of their respective owners. June 27, 1997
OPTi Inc. * 888 Tasman Drive * Milpitas, CA 95035 * (408) 486-8000
OPTi Inc.
888 Tasman Drive Milpitas, CA 95035 Tel: (408) 486-8000 Fax: (408) 486-8001 www.opti.com

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